Datasheet

Rev.6.00 Mar. 18, 2009 Page xxii of lviii
REJ09B0050-0600
2.7.8 Memory Indirect—@@aa:8 ................................................................................ 51
2.7.9 Effective Address Calculation ............................................................................. 52
2.8 Processing States............................................................................................................... 55
2.9 Usage Note........................................................................................................................ 56
2.9.1 Note on Bit Manipulation Instructions................................................................. 56
Section 3 MCU Operating Modes .................................................................................. 57
3.1
Operating Mode Selection ................................................................................................ 57
3.2 Register Descriptions ........................................................................................................ 58
3.2.1 Mode Control Register (MDCR) ......................................................................... 58
3.2.2 System Control Register (SYSCR) ...................................................................... 58
3.3 Operating Mode Descriptions ........................................................................................... 60
3.3.1 Mode 1 ................................................................................................................. 60
3.3.2 Mode 2 ................................................................................................................. 60
3.3.3 Mode 3 ................................................................................................................. 60
3.3.4 Mode 4 ................................................................................................................. 60
3.3.5 Mode 5 ................................................................................................................. 61
3.3.6 Mode 7 ................................................................................................................. 61
3.3.7 Pin Functions ....................................................................................................... 62
3.4 Memory Map in Each Operating Mode ............................................................................ 63
Section 4 Exception Handling ......................................................................................... 79
4.1
Exception Handling Types and Priority............................................................................ 79
4.2 Exception Sources and Exception Vector Table ............................................................... 79
4.3 Reset.................................................................................................................................. 81
4.3.1 Reset Exception Handling.................................................................................... 81
4.3.2 Interrupts after Reset............................................................................................ 83
4.3.3 On-Chip Peripheral Functions after Reset Release.............................................. 83
4.4 Traces................................................................................................................................ 84
4.5 Interrupts........................................................................................................................... 84
4.6 Trap Instruction................................................................................................................. 85
4.7 Stack Status after Exception Handling.............................................................................. 86
4.8 Usage Notes ...................................................................................................................... 87
Section 5 Interrupt Controller .......................................................................................... 89
5.1 Features............................................................................................................................. 89
5.2 Input/Output Pins.............................................................................................................. 91
5.3 Register Descriptions ........................................................................................................ 91
5.3.1 Interrupt Control Register (INTCR) .................................................................... 92
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 93