Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 177 of 980
REJ09B0050-0600
This LSI
(Address shift size
set to 10 bits)
RASn (CSn)
2-CAS type 16-Mbit DRAM
1-Mbyte × 16-bit configuration
10-bit column address
RAS
UCAS UCAS
LCAS
LCAS
HWR (WE)
WE
RD (OE) OE
A9
A8
A10 A9
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
D15 to D0 D15 to D0
Row address input:
A9 to A0
Column address input:
A9 to A0
Figure 6.28 Example of 2-CAS DRAM Connection
6.6.11 Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
Burst Access (Fast Page Mode): Figures 6.29 and 6.30 show the operation timing for burst
access. When there are consecutive access cycles for DRAM space, the CAS signal and column
address output cycles (two states) continue as long as the row address is the same for consecutive
access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in
DRAMCR.