Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 175 of 980
REJ09B0050-0600
By program wait
T
p
Address bus
φ
WAIT
T
r
T
c1
T
w
T
w
T
c2
T
c3
By WAIT pin
RASn (CSn)
Read
Write
UCAS, LCAS
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Row address Column address
High
High
Notes: Downward arrows indicate the timing of WAIT pin sampling.
n = 2, 3
Figure 6.26 Example of Wait State Insertion Timing
(3-State Column Address Output)