Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 169 of 980
REJ09B0050-0600
from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space,
the signal is output only from the RD pin.
6.6.6 Column Address Output Cycle Control
The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit
to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width,
etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.21
shows an example of the timing when a 3-state column address output cycle is selected.
T
p
φ
RASn (CSn)
Read
Write
UCAS, LCAS
WE
(HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Address bus
T
r
T
c1
T
c2
T
c3
Row address Column address
High
High
Note: n = 2, 3
Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0)