Datasheet
Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 167 of 980
REJ09B0050-0600
6.6.4 Pins Used for DRAM Interface
Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2, CS5 pins
are in the input state after a reset, set the corresponding DDR to 1 when RAS2, RAS5 signals are
output.
Table 6.6 DRAM Interface Pins
Pin
With DRAM
Setting
Name
I/O
Function
HWR WE Write enable Output Write enable for DRAM space
access
CS2 RAS2 Row address strobe 2/
row address strobe
Output Row address strobe when area
2 is designated as DRAM space
or row address strobe when
areas 2 to 5 are designated as
continuous DRAM space
CS3 RAS3 Row address strobe 3 Output Row address strobe when area
3 is designated as DRAM space
UCAS UCAS Upper column address
strobe
Output Upper column address strobe for
16-bit DRAM space access or
column address strobe for 8-bit
DRAM space access
LCAS LCAS Lower column address
strobe
Output Lower column address strobe
signal for 16-bit DRAM space
access
RD, OE OE Output enable Output Output enable signal for DRAM
space access
WAIT WAIT Wait Input Wait request signal
A15 to A0 A15 to A0 Address pins Output Row address/column address
multiplexed output
D15 to D0 D15 to D0 Data pins I/O Data input/output pins