Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 163 of 980
REJ09B0050-0600
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
T
3
Data bus
RD
DACK
Data bus
RDNn = 0
RDNn = 1
Figure 6.18 Example of Read Strobe Timing
6.5.6 Extension of Chip Select (CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.19 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.