Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 156 of 980
REJ09B0050-0600
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Invalid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
D7 to D0
Valid
Write
High
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)