Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 155 of 980
REJ09B0050-0600
16-Bit, 2-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be
inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Write
High
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access)