Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 153 of 980
REJ09B0050-0600
6.5.3 Basic Timing
8-Bit, 2-State Access Space: Figure 6.9 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
High impedance
Write
High
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.9 Bus Timing for 8-Bit, 2-State Access Space