Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 151 of 980
REJ09B0050-0600
D15 D8 D7 D0
Upper data bus Lower data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space)
16-Bit Access Space: Figure 6.8 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
D15 D8 D7 D0
Upper data bus Lower data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
• Even address
Byte size • Odd address
Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space)