Datasheet
Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 150 of 980
REJ09B0050-0600
Bus cycle
T
1
T
2
T
3
Area n external address
Address bus
Figure 6.6 CSn Signal Output Timing (n = 0 to 7)
6.5 Basic Bus Interface
The basic bus interface enables direct connection of ROM, SRAM, and so on.
6.5.1 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 6.7 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.