Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 143 of 980
REJ09B0050-0600
Bit Bit Name Initial Value R/W Description
3 SLFRF 0 R/W Self-Refresh Enable
If this bit is set to 1, DRAM self-refresh mode is
selected when a transition is made to the
software standby state. This bit is valid when
the RFSHE bit is set to 1, enabling refresh
operations. It is cleared after recovery from
software standby mode.
0: Self-refreshing is disabled
1: Self-refreshing is enabled
2
1
0
TPCS2
TPCS1
TPCS0
0
0
0
R/W
R/W
R/W
Self-Refresh Precharge Cycle Control
These bits select the number of states in the
precharge cycle immediately after self-
refreshing.
The number of states in the precharge cycle
immediately after self-refreshing are added to
the number of states set by bits TPC1 and
TPC0 in DRACCR.
000: [TPC set value] states
001: [TPC set value + 1] states
010: [TPC set value + 2] states
011: [TPC set value + 3] states
100: [TPC set value + 4] states
101: [TPC set value + 5] states
110: [TPC set value + 6] states
111: [TPC set value + 7] states