Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 140 of 980
REJ09B0050-0600
6.3.9 DRAM Access Control Register (DRACCR)
DRACCR is used to set the DRAM interface bus specifications.
Bit Bit Name Initial Value R/W Description
7 DRMI 0 R/W Idle Cycle Insertion
An idle cycle can be inserted after a DRAM
access cycle when a continuous normal space
access cycle follows a DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
6 − 0 R/W Reserved
Though this bit can be read from or written to,
the write value should always be 0.
5
4
TPC1
TPC0
0
0
R/W
R/W
Precharge State Control
These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.
00: 1-state RAS precharge cycle
01: 2-state RAS precharge cycle
10: 3-state RAS precharge cycle
11: 4-state RAS precharge cycle
3, 2 — All 0 R/W Reserved
Though these bits can be read from or written to,
the write value should always be 0.
1
0
RCD1
RCD0
0
0
R/W
R/W
RAS-CAS Wait Control
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle. A 1- to 4-state wait cycle can be inserted.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted