
Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 139 of 980
REJ09B0050-0600
T
p
Address
φ
RAST = 0 RAS
RAST = 1 RAS
T
r
T
c1
T
c2
UCAS, LCAS
Bus cycle
Row address Column address
Figure 6.4 RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)