Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 138 of 980
REJ09B0050-0600
Bit Bit Name Initial Value R/W Description
2
1
0
MXC2
MXC1
MXC0
0
0
0
R/W
R/W
R/W
Address Multiplex Select
These bits select the size of the shift toward the
lower half of the row address in row
address/column address multiplexing. In burst
operation on the DRAM interface, these bits also
select the row address bits to be used for
comparison.
For details, refer to section 6.6.2, Address
Multiplexing.
000: 8-bit shift
When 8-bit access space is designated:
Row address bits A23 to A8 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A9 used for
comparison
001: 9-bit shift
When 8-bit access space is designated:
Row address bits A23 to A9 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A10 used for
comparison
010: 10-bit shift
When 8-bit access space is designated:
Row address bits A23 to A10 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A11 used for
comparison
011: 11-bit shift
When 8-bit access space is designated:
Row address bits A23 to A11 used for
comparison
When 16-bit access space is designated:
Row address bits A23 to A12 used for
comparison
1××: Setting prohibited
Legend:
×: Don't care