Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 135 of 980
REJ09B0050-0600
6.3.8 DRAM Control Register (DRAMCR)
DRAMCR is used to make DRAM/synchronous DRAM interface settings.
Bit Bit Name Initial Value R/W Description
15 OEE 0 R/W OE Output Enable
The OE signal used when EDO page mode
DRAM is connected can be output from the
(OE) pin. The OE signal is common to all
areas designated as DRAM space.
0: OE signal output disabled
(OE) pin can be used as I/O port
1: OE signal output enabled
14 RAST 0 R/W RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS
signal is asserted from the start of the T
r
cycle
(rising edge of φ) or from the falling edge of φ.
Figure 6.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from φ falling edge in T
r
cycle
1: RAS is asserted from start of T
r
cycle
13 − 0 R/W Reserved
Though this bit can be read from or written to,
the write value should always be 0.
12 CAST 0 R/W Column Address Output Cycle Number Select
Selects whether the column address output
cycle in DRAM access comprises 3 states or 2
states. The setting of this bit applies to all
areas designated as DRAM space.
0: 2-state column address output cycle
1: 3-state column address output cycle
11 − 0 R/W Reserved
Though this bit can be read from or written to,
the write value should always be 0.