
Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 131 of 980
REJ09B0050-0600
T
h
Address
φ
T
1
T
2
T
3
T
t
Bus cycle
Data
HWR, LWR
Write
Data
RD
CS
Read
Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space
and RDNn = 0)