Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 122 of 980
REJ09B0050-0600
Name Symbol I/O Function
Lower column address strobe LCAS Output 16-bit DRAM space lower column address
strobe signal.
Output enable OE Output Output enable signal for the DRAM space.
Wait WAIT Input Wait request signal when accessing
external address space.
Bus request BREQ Input Request signal for release of bus to
external bus master.
Bus request acknowledge BACK Output Acknowledge signal indicating that bus has
been released to external bus master.
Bus request output BREQO Output External bus request signal used when
internal bus master accesses external
address space when external bus is
released.
Data transfer acknowledge
1 (DMAC)
DACK1 Output Data transfer acknowledge signal for single
address transfer by DMAC channel 1.
Data transfer acknowledge
0 (DMAC)
DACK0 Output Data transfer acknowledge signal for single
address transfer by DMAC channel 0.
6.3 Register Descriptions
The bus controller has the following registers.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register AH (WTCRAH)
• Wait control register AL (WTCRAL)
• Wait control register BH (WTCRBH)
• Wait control register BL (WTCRBL)
• Read strobe timing control register (RDNCR)
• CS assertion period control register H (CSACRH)
• CS assertion period control register L (CSACRL)
• Area 0 burst ROM interface control register (BROMCRH)
• Area 1 burst ROM interface control register (BROMCRL)
• Bus control register (BCR)
• DRAM control register (DRAMCR)
• DRAM access control register (DRACCR)