Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 121 of 980
REJ09B0050-0600
6.2 Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1 Pin Configuration
Name Symbol I/O Function
Address strobe AS Output Strobe signal indicating that normal space
is accessed and address output on
address bus is enabled.
Read RD Output Strobe signal indicating that normal space
is being read.
High write HWR Output Strobe signal indicating that normal space
is written to, and upper half (D15 to D8) of
data bus is enabled or DRAM space write
enable signal.
Low write LWR Output Strobe signal indicating that normal space
is written to, and lower half (D7 to D0) of
data bus is enabled.
Chip select 0 CS0 Output Strobe signal indicating that area 0 is
selected.
Chip select 1 CS1 Output Strobe signal indicating that area 1 is
selected
Chip select 2/row address
strobe 2
CS2/
RAS2
Output Strobe signal indicating that area 2 is
selected, DRAM row address strobe signal
when area 2 is DRAM space or areas 2 to
5 are set as continuous DRAM space.
Chip select 3/row address
strobe 3
CS3/
RAS3
Output Strobe signal indicating that area 3 is
selected, DRAM row address strobe signal
when area 3 is DRAM space.
Chip select 4 CS4 Output Strobe signal indicating that area 4 is
selected.
Chip select 5 CS5 Output Strobe signal indicating that area 5 is
selected.
Chip select 6 CS6 Output Strobe signal indicating that area 6 is
selected.
Chip select 7 CS7 Output Strobe signal indicating that area 7 is
selected.
Upper column address strobe UCAS Output 16-bit DRAM space upper column address
strobe signal, 8-bit DRAM space column
address strobe signal.