Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 120 of 980
REJ09B0050-0600
A block diagram of the bus controller is shown in figure 6.1.
Area decoder
Internal address bus
CS7 to CS0
WAIT
BREQ
BACK
BREQO
External bus
control signals
Internal bus control signals
Internal data bus
Control registers
External bus
arbiter
External bus controller
Internal bus
arbiter
Internal bus controller
Internal bus master bus request signal
Internal bus master bus acknowledge signal
CPU bus request signal
DTC bus request signal
DMAC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
DMAC bus acknowledge signal
ABWCR ASTCR
WTCRAH WTCRAL
WTCRBH WTCRBL
RDNCR
DRAMCR
Legend:
ABWCR: Bus width control register
ASTCR: Access state control register
WTCRAH, WTCRAL,
WTCRBH, and WTCRBL: Wait control registers AH, AL, BH, and BL
RDNCR: Read strobe timing control register
CSACRH and CSACRL: CS assertion period control registers H and L
BROMCRH: Area 0 burst ROM interface control register
BROMCRL: Area 1 burst ROM interface control register
BCR: Bus control register
DRAMCR: DRAM control register
DRACCR: DRAM access control register
REFCR: Refresh control register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
REFCR
RTCNT RTCOR
CSACRH CSACRL
BROMCRH BROMCRL
BCR
DRACCR
Figure 6.1 Block Diagram of Bus Controller