Datasheet

Section 6 Bus Controller (BSC)
Rev.6.00 Mar. 18, 2009 Page 119 of 980
REJ09B0050-0600
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external space divided into eight
areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
masters—the CPU, DMA controller (DMAC) and data transfer controller (DTC).
6.1 Features
Manages external space in area units
Manages the external space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, or DRAM, interface can be set
Basic bus interface
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
Burst ROM interface
Burst ROM interface can be set independently for areas 0 and 1
DRAM interface
DRAM interface can be set for areas 2 to 5
Bus arbitration function
Includes a bus arbiter that arbitrates bus right between the CPU, DMAC, and DTC
BSCS201A_000020020100