Datasheet

Rev.6.00 Mar. 18, 2009 Page xv of lviii
REJ09B0050-0600
Item Page Revision (See Manual for Details)
15.7 Usage Notes
3. I
2
C bus interface 2
(IIC2) master receive
mode
4. Limitations on transfer
rate setting values when
using I
2
C bus interface 2
(IIC2) in multi-master
mode
5. Limitations on use of
bit manipulation
instructions to set MST
and TRS when using I
2
C
bus interface 2 (IIC2) in
multi-master mode
660 Description added
16.1 Features
Figure 16.1 Block
Diagram of A/D Converter
662 Figure amended
10-bit D/A
AVCC
Vref
AVSS
20.3.2 Programming/
Erasing Interface
Parameter
735 Description amended
… The return value of the processing result is written in ER0,
ER1. Since the stack area is used for storing the registers except
for ER0, ER1, the stack area must be saved at the processing
start.
20.3.3 Flash Vector
Address Control Register
(FVACR)
747 Description amended
… Normally the vector table data is read from the address
spaces from H'00001C to H'00001F.
20.4.2 User Program
Mode
(2) Programming
Procedure in User
Program Mode
757 Description amended
The notes on download are as follows.
⎯ In the download processing, the values of CPU general
registers other than ER0 and ER1 are retained.