Datasheet

Section 5 Interrupt Controller
Rev.6.00 Mar. 18, 2009 Page 109 of 980
REJ09B0050-0600
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution status
Interrupt generated?
NMI
IRQ0
IRQ1
IICI1
I = 0
Save PC and CCR
I ← 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Hold
pending
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0