Datasheet

Section 5 Interrupt Controller
Rev.6.00 Mar. 18, 2009 Page 101 of 980
REJ09B0050-0600
5.3.7 Software Standby Release IRQ Enable Register (SSIER)
SSIER selects the IRQ pins used to recover from the software standby state.
Bit Bit Name Initial Value R/W Description
15 to 8 — All 0 R/W Reserved
The write value should always be 0.
7
6
5
4
3
2
1
0
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Software Standby Release IRQ Setting
These bits select the IRQn pins used to
recover from the software standby state.
0: IRQn requests are not sampled in the
software standby state (Initial value when n
= 7 to 3)
1: When an IRQn request occurs in the
software standby state, the chip recovers
from the software standby state after the
elapse of the oscillation settling time (Initial
value when n = 2 to 0)
5.4 Interrupt Sources
5.4.1 External Interrupts
There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore
the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
• Using ISCRL, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.