Datasheet

Section 5 Interrupt Controller
Rev.6.00 Mar. 18, 2009 Page 99 of 980
REJ09B0050-0600
5.3.5 IRQ Status Register (ISR)
ISR is an IRQ7 to IRQ0 interrupt request flag register.
Bit
Bit
Name Initial Value R/W Description
15 to 8 − All 0 R/W Reserved
The write value should always be 0.
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
[Setting condition]
When the interrupt source selected by ISCR
occurs
[Clearing conditions]
• Cleared by reading IRQnF flag when
IRQnF = 1, then writing 0 to IRQnF flag
• When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high
• When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
• When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
Note: * Only 0 can be written, to clear the flag.