Datasheet

Section 5 Interrupt Controller
Rev.6.00 Mar. 18, 2009 Page 95 of 980
REJ09B0050-0600
5.3.3 IRQ Enable Register (IER)
IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit Bit Name Initial Value R/W Description
15 to
8
− All 0 R/W Reserved
The write value should always be 0.
7 IRQ7E 0 R/W IRQ7 Enable
The IRQ7 interrupt request is enabled when this
bit is 1.
6 IRQ6E 0 R/W IRQ6 Enable
The IRQ6 interrupt request is enabled when this
bit is 1.
5 IRQ5E 0 R/W IRQ5 Enable
The IRQ5 interrupt request is enabled when this
bit is 1.
4 IRQ4E 0 R/W IRQ4 Enable
The IRQ4 interrupt request is enabled when this
bit is 1.
3 IRQ3E 0 R/W IRQ3 Enable
The IRQ3 interrupt request is enabled when this
bit is 1.
2 IRQ2E 0 R/W IRQ2 Enable
The IRQ2 interrupt request is enabled when this
bit is 1.
1 IRQ1E 0 R/W IRQ1 Enable
The IRQ1 interrupt request is enabled when this
bit is 1.
0 IRQ0E 0 R/W IRQ0 Enable
The IRQ0 interrupt request is enabled when this
bit is 1.