Datasheet

Section 5 Interrupt Controller
Rev.6.00 Mar. 18, 2009 Page 93 of 980
REJ09B0050-0600
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK)
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a
value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0
sets the priority of the corresponding interrupt. IPR should be read in word size.
Bit Bit Name Initial Value R/W Description
15
− 0 − Reserved
This bit is always read as 0 and cannot be
modified.
14
13
12
IPR14
IPR13
IPR12
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
11
− 0 − Reserved
This bit is always read as 0 and cannot be
modified.
10
9
8
IPR10
IPR9
IPR8
1
1
1
R/W
R/W
R/W
Sets the priority of the corresponding interrupt
source.
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
7 − 0 − Reserved
This bit is always read as 0 and cannot be
modified.