Datasheet

Section 5 Interrupt Controller
Rev.6.00 Mar. 18, 2009 Page 90 of 980
REJ09B0050-0600
A block diagram of the interrupt controller is shown in figure 5.1.
INTCR
NMI input
IRQ input
Internal
interrupt
sources
SWDTEND
to IICI1
INTM1 INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCRLITSR IER
IPR
Interrupt controller
Priority
determination
Interrupt
request
Vector
number
I
I2 to I0
CCR
EXR
CPU
Legend:
ISCRL: IRQ sense control register
IER: IRQ enable register
ISR: IRQ status register
IPR: Interrupt priority register
INTCR: Interrupt control register
ITSR: IRQ pin select register
SSIER: Software standby release IRQ enable register
SSIER
Figure 5.1 Block Diagram of Interrupt Controller