Datasheet

Rev.6.00 Mar. 18, 2009 Page xiii of lviii
REJ09B0050-0600
Item Page Revision (See Manual for Details)
15.3.1 I
2
C Bus Control
Register A (ICCRA)
Table 15.2 Transfer Rate
634 Note amended
Notes: 2. Does not conform to the I
2
C bus interface
specification (standard mode: max. 100 kHz, fast
mode: max. 400 kHz).
15.3.5 I
2
C Bus Status
Register (ICSR)
639 Table amended
Bit Bit Name Initial Value R/W Description
7 TDRE 0 R/W Transmit Data Register Empty
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When a transition from receive mode to transmit mode is
made in slave mode
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT
15.4.5 Slave Receive
Operation
Figure 15.12 Slave
Receive Mode Operation
Timing 2
652 Figure amended
ICDRS
ICDRR
12345678 99
A
A
RDRF
SCL
(master output)
SDA
(master output)
SDA
(slave output)
SCL
(slave output)
User
processing
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[7] Set ACKBT
[8] Read ICDRR,
and clear RDRF.
[10] Read ICDRR,
and clear RDRF.
Data 2
Data 1
15.4.7 Example of Use
Figure 15.14 Sample
Flowchart for Master
Transmit Mode
654 Figure amended
BBSY=0 ?
No
Yes
Start
[1]
[2]
[3]
Initialize
Set MST = 1 and TRS
= 1 in ICCRA.
Write BBSY = 1
and SCP = 0.
Read BBSY in ICCRB
[1] Test the status of the SCL and SDA lines.*
[2] Select master transmit mode.*
[3] Start condition issuance.*
[4] Select transmit data for the first byte (slave address + R/W),
and clear TDRE to 0.
Note: * Ensure that no interrupts occur between
when BBSY is cleared to 0 and start condition [3].