Datasheet

Section 5 Interrupt Controller
Rev.6.00 Mar. 18, 2009 Page 89 of 980
REJ09B0050-0600
Section 5 Interrupt Controller
5.1 Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
interrupt control register (INTCR).
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the highest
priority level of 8, and can be accepted at all times.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Nine external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level sensing,
can be selected for IRQ7 to IRQ0.
• DTC and DMAC control
DTC and DMAC activations are performed by means of interrupts.