Datasheet

Section 4 Exception Handling
Rev.6.00 Mar. 18, 2009 Page 82 of 980
REJ09B0050-0600
High
Vector fetch
Internal
processing
Prefetch of first
program instruction
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1)
(2) (4) (6)
(3) (5)
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)