Datasheet

Rev.6.00 Mar. 18, 2009 Page xii of lviii
REJ09B0050-0600
Item Page Revision (See Manual for Details)
14.3.9 Bit Rate Register
(BRR)
Table 14.3 BRR Settings
for Various Bit Rates
(Asynchronous Mode)
566
Table amended
Operating Frequency φ
φ
(MHz)
17.2032 18 19.6608 20
Bit Rate
(bit/s) n N
Error
(%) n N
Error
(%) n N
Error
(%) n N
Error
(%)
19200 0 27 0.00 0 28 1.02 0 31 0.00 0 32 –1.36
31250 0 16 1.20 0 17 0.00 0 19 –1.70 0 19 0.00
38400 0 13 0.00 0 14 –2.34 0 15 0.00 0 15 1.73
Operating Frequency
φ
(MHz)
25 30 33 34
*
Bit Rate
(bit/s)
n N
Error
(%) n N
Error
(%) n N
Error
(%) n N
Error
(%)
19200 0 40 –0.76 0 48 –0.35 0 53 –0.54 0 54 0.62
31250 0 24 0.00 0 29 0 0 32 0 0 33 0.00
38400 0 19 1.73 0 23 1.73 0 26 –0.54 0 27 –1.18
14.4.4 SCI Initialization
(Asynchronous Mode)
580 Description amended
... Do not write to SMR, SCMR, IrCR, or SEMR while the SCI is
operating. This also applies to writing the same data as the
current register contents. ...
14.6.2 SCI Initialization
(Clocked Synchronous
Mode)
596 Description amended
... Do not write to SMR, SCMR, IrCR, or SEMR while the SCI is
operating. This also applies to writing the same data as the
current register contents. ...
Section 15 I
2
C Bus
Interface2 (IIC2) (Option)
629 Description amended
The I
2
C bus interface conforms to and provides a subset of the
NXP Semiconductors I
2
C bus (inter-IC bus) interface (Rev.03)
standard and fast mode functions. The register configuration that
controls the I
2
C bus differs partly from the NXP Semiconductors
configuration, however.