Datasheet

Section 3 MCU Operating Modes
Rev.6.00 Mar. 18, 2009 Page 60 of 980
REJ09B0050-0600
3.3 Operating Mode Descriptions
3.3.1 Mode 1
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F, and G, carry bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for all areas by the bus controller, the bus mode switches to 8 bits.
3.3.2 Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F, and G carry bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any one of the areas by the bus controller, the bus mode switches to 16 bits and
port E functions as a data bus.
3.3.3 Mode 3
This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for the
programming and erasure on the flash memory. Mode 3 is only available in the H8S/2368 Group
flash memory version.
3.3.4 Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in the on-chip ROM connected to the first half of area 0 is executed.
Ports A, B, and C function as input ports immediately after a reset, but can be set to function as an
address bus. Ports D and E function as a data bus, and parts of ports F, and G, carry bus control
signals. For details, see section 9, I/O Ports.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any area by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus.