Datasheet

Section 2 CPU
Rev.6.00 Mar. 18, 2009 Page 56 of 980
REJ09B0050-0600
Exception
handling state
Bus-released state
Software standby
mode
Reset state*
1
Sleep mode
Power down state*
3
Program execution state
End of bus request
Bus request
RES = High
STBY = High,
RES = Low
Reset state
Hardware standby
mode*
2
End of bus request
Bus request
Request for exception handling
Interrupt request
External interrupt request
SSBY = 0
SLEEP
instruction
SSBY = 1
SLEEP instruction
End of exception handling
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.
A transition can also be made to the reset state when the watchdog timer overflows.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 23, Power-Down Modes.
Figure 2.13 State Transitions
2.9 Usage Note
2.9.1 Note on Bit Manipulation Instructions
Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte
units, perform bit manipulation, and write data in byte units. Thus, care must be taken when these
bit manipulation instructions are executed for a register or port including write-only bits.
In addition, the BCLR instruction can be used to clear the flag of an internal I/O register. In this
case, if the flag to be cleared has been set by an interrupt processing routine, the flag need not be
read before executing the BCLR instruction.