Datasheet

Section 2 CPU
Rev.6.00 Mar. 18, 2009 Page 52 of 980
REJ09B0050-0600
Note that the top area of the address range in which the branch address is stored is also used for
the exception vector area. For further details, refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or the instruction code to be
fetched at the address preceding the specified address. (For further information, see section 2.5.2,
Memory Data Formats.)
Specified
by @aa:8
Specified
by @aa:8
Branch address
Branch address
Reserved
(a) Normal Mode * (b) Advanced Mode
Note: * For this LSI, normal mode is not available.
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.