Datasheet

Rev.6.00 Mar. 18, 2009 Page ix of lviii
REJ09B0050-0600
Item Page Revision (See Manual for Details)
3.4 Memory Map in Each
Operating Mode
Figure 3.5 H8S/2364F
Memory Map (1)
67 Figure amended
RAM: 32 kbytes
Modes 1 and 2
(Expanded mode with
on-chip ROM disabled)
ROM: 384 kbytes
RAM: 32 kbytes
Mode 3
(Boot mode)
H'000000
H'FF4000
H'FFC000
H'FFD000
H'000000
H'FFFC00
External address
space
On-chip RAM/
external address
space
*
1
On-chip RAM
*
3
External address space
External address space
Internal I/O registers
On-chip ROM
Reserved area
*
4
H'FFFFFF
H'FFFC00
H'FFFF00
H'FFFF20
H'FFFFFF
H'FFFF00
H'FFFF20
H'080000
H'060000
External address
space/
reserved area
*
2
*
4
Reserved area
*
4
H'FF4000
H'FFC000
H'FFD000
Reserved area
*
4
Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. On-chip RAM is used for flash memory programming. The RAME bit in SYSCR should not be cleared to 0.
4. A reserved area should not be accessed.
Internal I/O registers
Internal I/O registers
Internal I/O registers
External address space/
reserved area
*
2
*
4
External address space/
reserved area
*
2
*
4
7.3.7 DMA Terminal
Control Register
(DMATCR)
240 Description amended
In short address mode, the TEND pin is only available for
channel B.
8.8.5 Chain Transfer 321 Description amended
When chain transfer is used, clearing of the activation source or
DTCER is performed when the last of the chain of data transfers
is executed. SCI and A/D converter
interrupt/activation sources, on the other hand, are cleared when
the DTC reads or writes to the prescribed register.