Datasheet

Appendix
Rev.6.00 Mar. 18, 2009 Page 953 of 980
REJ09B0050-0600
RD
HWR, LWR
Address bus
R: W 2nd R: W EA
High
Internal
operation
Fetch of 3rd byte of
instruction being
executed
Fetch of 4th byte of
instruction being
executed
Fetch of 1st byte of
brunch destination
instruction
Fetch of 2nd byte of
brunch destination
instruction
φ
Figure D.1 Timing of Address Bus, RD, HWR, and LWR (8-bit bus, 3-state access, no wait)