Datasheet

Appendix
Rev.6.00 Mar. 18, 2009 Page 952 of 980
REJ09B0050-0600
D. Bus State during Execution of Instructions
Table D.1 shows the execution state of each instruction in this LSI.
R:W 2nd
1 state of inter-
nal operation
R:W EA
Order of execution
End of instruction
Read the effective address in words.
Read/write is not performed.
Read the second word of the instruction that is being executed in words.
1Instruction
[Explanation of Table Contents]
2345678
Legend:
R:B Reading in bytes
R:W Reading in words
W:B Writing in bytes
W:W Writing in words
:M Bus right cannot be handed over immediately after this cycle
2nd Address of second word (3rd and 4th bytes)
3rd Address of third word (5th and 6th bytes)
4th Address of fourth word (7th and 8th bytes)
5th Address of fifth word (9th and 10th bytes)
NEXT Start address of instruction immediately following the instruction being executed
EA Effective address
VEC Vector address
Figure D.1 shows the timing of the address bus, RD, HWR, and LWR during execution of the
sample instruction above (example in "Explanation of Table Contents") with an 8-bit bus, 3-state
access, and no wait.