Datasheet

Appendix
Rev.6.00 Mar. 18, 2009 Page 948 of 980
REJ09B0050-0600
Port Name
MCU
Operating
Mode
Reset
Hardware
Standby
Mode
Software
Standby Mode
Bus Release
State
Program
Execution
State Sleep
Mode
1, 2 H
3, 4, 7 T
PG0/CS0 T [OPE = 0,
CS output]
T
[OPE = 1,
CS output]
H
[Other than the
above]
Keep
[CS output]
T
[Other than the
above]
Keep
[CS output]
CS
[Other than
the above]
I/O port
WDTOVF 1, 2, 3, 4,
7
H H H H H
*
Legend:
L: Low level
H: High level
Keep: Input port becomes high-impedance, output port retains state
T: High impedance
DDR: Data direction register
OPE: Output port enable
Notes: Indicates the state after the bus cycle being executed is completed.
* Low output if a watchdog overflow occurs when WT/IT is set to 1.