To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2368 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series H8S/2368F H8S/2367F H8S/2365 H8S/2364F H8S/2363 H8S/2362F H8S/2361F H8S/2360F HD64F2368 HD64F2367 HD6432365 HD64F2364 HD6412363 HD64F2362 HD64F2361 HD64F2360 Rev.6.00 2009.
Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2.
General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. General Precautions in the Handling of MPU/MCU Products Configuration of This Manual Preface Main Revisions for This Edition The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 5. Contents 6. Overview 7.
Preface The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas Technology’s original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a 16-Mbyte linear address space.
• In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Software Manual. For the execution state of each instruction in this LSI, see appendix D, Bus State during Execution of Instructions. • In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register.
Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.3.3 Pin Functions 14 Table amended Pin No. Table 1.2 Pin Functions Type I/O Function Input Power supply pins. VCC pins should be connected to the system power supply. Vss 8, 17, 22, 58, 80, 87 3,4,12,21, 26,35,36, 64,68,88, 95,99,100 Input Ground pins. VSS pins should be connected to the system power supply (0 V). PLLVCC 76 84 Input Power supply pin for the on-chip PLL oscillator.
Item Page Revision (See Manual for Details) 3.4 Memory Map in Each 64 Operating Mode Figure amended ROM: 512 kbytes RAM: 32 kbytes Mode 5 (User boot mode) ROM: 512 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) Figure 3.
Item Page Revision (See Manual for Details) 3.4 Memory Map in Each 67 Operating Mode Figure amended ROM: 384 kbytes RAM: 32 kbytes Mode 3 (Boot mode) RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) Figure 3.
Item Page Revision (See Manual for Details) 9.8.
Item Page Revision (See Manual for Details) 9.13.4 Pin Functions 391 Table amended • PF7/φ (Before) PFDDR → (After) PF7DDR 393 Table amended • PF1/CS5/UCAS PF1DDR — 14.3.7 Serial Status Register (SSR) 558 Note: 562 14.3.9 Bit Rate Register 565 (BRR) Table 14.
Item Page Revision (See Manual for Details) 14.3.9 Bit Rate Register 566 (BRR) Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Table amended Operating Frequency φ (MHz) 17.2032 Bit Rate (bit/s) n 19200 31250 38400 18 N Error (%) n 0 27 0.00 0 16 1.20 0 13 0.00 19.6608 N Error (%) n 0 28 1.02 0 17 0.00 0 14 –2.34 20 N Error (%) n N Error (%) 0 31 0.00 0 32 –1.36 0 19 –1.70 0 19 0.00 0 15 0.00 0 15 1.
Item Page Revision (See Manual for Details) 2 15.3.1 I C Bus Control Register A (ICCRA) 634 Notes: 2. Does not conform to the I2C bus interface specification (standard mode: max. 100 kHz, fast mode: max. 400 kHz). Table 15.2 Transfer Rate 15.3.
Item Page Revision (See Manual for Details) 15.4.7 Example of Use 655 Figure amended Figure 15.15 Sample Flowchart for Master Receive Mode Read ICDRR [8] [16] Set slave receive mode. Read RDRF in ICSR No [15] Clear ACKBT.
Item Page Revision (See Manual for Details) 15.7 Usage Notes 660 Description added 662 Figure amended 2 3. I C bus interface 2 (IIC2) master receive mode 4. Limitations on transfer rate setting values when using I2C bus interface 2 (IIC2) in multi-master mode 5. Limitations on use of bit manipulation instructions to set MST and TRS when using I2C bus interface 2 (IIC2) in multi-master mode 16.1 Features Figure 16.1 Block Diagram of A/D Converter AVCC Vref 10-bit D/A AVSS 20.3.
Item Page Revision (See Manual for Details) 788 20.8 Serial Communication Interface Specification for Boot Mode (b) Device Selection … • (4) Inquiry and Selection States Figure 20.
Item Page Revision (See Manual for Details) 25.1.2 DC Characteristics 876 Item Table 25.4 Permissible Output Currents 25.2.2 DC Characteristics Table amended SCL0, 1, SDA0, 1 Permissible output low current (per pin) 912 Table 25.14 DC Characteristics (1) Symbol Min Typ Max Unit IOL ⎯ ⎯ 8.0 mA ⎯ ⎯ 2.0 Output pins other than the above Table amended Item Symbol Min Typ Schmitt Ports 1, 2, and 4* , VT VCC × 0.
Item Page Revision (See Manual for Details) 25.3.2 DC Characteristics 927 Table 25.
Item Page Revision (See Manual for Details) 25.3.3 AC Characteristics 930 Description deleted (Before) The clock, control signal, bus, DMAC, and … (After) The clock, control signal, bus, DMAC, and … 25.3.3 AC Characteristics Table 25.33 Bus Timing (2) 935 Table amended Item Symbol Min. WAIT hold time tWTH 5 Rev.6.00 Mar.
All trademarks and registered trademarks are the property of their respective owners. Rev.6.00 Mar.
Contents Section 1 Overview ............................................................................................................. 1.1 1.2 1.3 1 Features ............................................................................................................................. 1 Block Diagram .................................................................................................................. 3 Pin Description............................................................................
2.8 2.9 2.7.8 Memory Indirect—@@aa:8 ................................................................................ 2.7.9 Effective Address Calculation ............................................................................. Processing States............................................................................................................... Usage Note........................................................................................................................ 2.9.
5.4 5.5 5.6 5.7 5.3.3 IRQ Enable Register (IER) .................................................................................. 5.3.4 IRQ Sense Control Register L (ISCRL)............................................................... 5.3.5 IRQ Status Register (ISR).................................................................................... 5.3.6 IRQ Pin Select Register (ITSR) ........................................................................... 5.3.
6.3.12 Refresh Time Constant Register (RTCOR) ......................................................... Operation .......................................................................................................................... 6.4.1 Area Division....................................................................................................... 6.4.2 Bus Specifications................................................................................................ 6.4.3 Memory Interfaces .......
6.11.1 Operation ............................................................................................................. 6.11.2 Bus Transfer Timing ............................................................................................ 6.12 Bus Controller Operation in Reset .................................................................................... 6.13 Usage Notes ...................................................................................................................... 6.13.
7.6 7.7 7.5.16 Clearing Full Address Mode................................................................................ Interrupt Sources............................................................................................................... Usage Notes ...................................................................................................................... 7.7.1 DMAC Register Access during Operation........................................................... 7.7.2 Module Stop.........
8.8 8.7.4 Software Activation ............................................................................................. Usage Notes ...................................................................................................................... 8.8.1 Module Stop Mode Setting .................................................................................. 8.8.2 On-Chip RAM ..................................................................................................... 8.8.
9.7.1 Port 9 Register (PORT9)...................................................................................... 9.7.2 Pin Functions ....................................................................................................... 9.8 Port A................................................................................................................................ 9.8.1 Port A Data Direction Register (PADDR) ........................................................... 9.8.
9.13 Port F................................................................................................................................. 9.13.1 Port F Data Direction Register (PFDDR) ............................................................ 9.13.2 Port F Data Register (PFDR) ............................................................................... 9.13.3 Port F Register (PORTF) ..................................................................................... 9.13.4 Pin Functions ...........
10.10.2 Input Clock Restrictions ...................................................................................... 10.10.3 Caution on Cycle Setting ..................................................................................... 10.10.4 Contention between TCNT Write and Clear Operations ..................................... 10.10.5 Contention between TCNT Write and Increment Operations.............................. 10.10.6 Contention between TGR Write and Compare Match ............................
12.3 Register Descriptions ........................................................................................................ 12.3.1 Timer Counter (TCNT)........................................................................................ 12.3.2 Time Constant Register A (TCORA)................................................................... 12.3.3 Time Constant Register B (TCORB) ................................................................... 12.3.4 Timer Control Register (TCR) .............
13.5 Interrupts........................................................................................................................... 536 13.6 Usage Notes ...................................................................................................................... 536 13.6.1 Notes on Register Access..................................................................................... 536 13.6.2 Contention between Timer Counter (TCNT) Write and Increment ..................... 538 13.6.
14.7 14.8 14.9 14.10 14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) ............................................................................. Operation in Smart Card Interface Mode .......................................................................... 14.7.1 Pin Connection Example...................................................................................... 14.7.2 Data Format (Except for Block Transfer Mode) ..........................................
15.4.2 Master Transmit Operation .................................................................................. 15.4.3 Master Receive Operation.................................................................................... 15.4.4 Slave Transmit Operation .................................................................................... 15.4.5 Slave Receive Operation...................................................................................... 15.4.6 Noise Canceler.........................
17.5.1 Setting for Module Stop Mode............................................................................. 686 17.5.2 D/A Output Hold Function in Software Standby Mode....................................... 686 Section 18 RAM .................................................................................................................. 687 Section 19 Flash Memory (0.35-μm F-ZTAT Version) ........................................... 689 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 19.10 19.
20.4 20.5 20.6 20.7 20.8 20.9 20.3.2 Programming/Erasing Interface Parameter .......................................................... 20.3.3 Flash Vector Address Control Register (FVACR)............................................... On-Board Programming Mode ......................................................................................... 20.4.1 Boot Mode ........................................................................................................... 20.4.2 User Program Mode........
23.2.2 Sleep Mode .......................................................................................................... 23.2.3 Software Standby Mode....................................................................................... 23.2.4 Hardware Standby Mode ..................................................................................... 23.2.5 Module Stop Mode .............................................................................................. 23.2.6 All-Module-Clocks-Stop Mode ..
Appendix A. B. C. D. ............................................................................................................................. I/O Port States in Each Pin State....................................................................................... Product Lineup.................................................................................................................. Package Dimensions ...............................................................................................
Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2367F, H8S/2365, and H8S/2363........................ Figure 1.2 Internal Block Diagram of H8S/2368 0.18 μm F-ZTAT Group............................. Figure 1.3 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363 .................................. Figure 1.4 Pin Arrangement of H8S/2368 0.18 μm F-ZTAT Group ....................................... Figure 1.5 Pin Arrangement of H8S/2367F, H8S/2365, and H8S/2363 ...............................
Figure 3.14 H8S/2365 Memory Map (2) ................................................................................... 76 Figure 3.15 H8S/2363 Memory Map......................................................................................... 77 Section 4 Exception Handling Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled).......................... Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled)......................... Figure 4.3 Stack Status after Exception Handling .
Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended .................... Figure 6.20 DRAM Basic Access Timing (RAST = 0, CAST = 0)........................................... Figure 6.21 Example of Access Timing with 3-State Column Address Output Cycle (RAST = 0)............................................................................................................. Figure 6.22 Example of Access Timing when RAS Signal Goes Low from Beginning of Tr State (CAST = 0) ................
Figure 6.52 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0)......................................................................... Figure 6.53 Example of Idle Cycle Operation after DRAM Write Access (IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0) ....................................................... Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode ............................
Figure 7.30 Figure 7.31 Figure 7.32 Figure 7.33 Figure 7.34 Figure 7.35 Figure 7.36 Figure 7.37 Figure 7.38 Figure 7.39 Figure 7.40 Figure 7.41 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer.... Example of DREQ Pin Low Level Activated Single Address Mode Transfer....... Example of Dual Address Transfer Using Write Data Buffer Function................. Example of Single Address Transfer Using Write Data Buffer Function .............. Example of Multi-Channel Transfer ...............
Figure 10.10 Example of Synchronous Operation Setting Procedure ......................................... Figure 10.11 Example of Synchronous Operation....................................................................... Figure 10.12 Compare Match Buffer Operation.......................................................................... Figure 10.13 Input Capture Buffer Operation ............................................................................. Figure 10.
Figure 10.50 Contention between TGR Write and Input Capture ............................................... Figure 10.51 Contention between Buffer Register Write and Input Capture............................... Figure 10.52 Contention between Overflow and Counter Clearing ............................................ Figure 10.53 Contention between TCNT Write and Overflow.................................................... 482 483 483 484 Section 11 Programmable Pulse Generator (PPG) Figure 11.
Section 14 Serial Communication Interface (SCI, IrDA) Figure 14.1 Block Diagram of SCI............................................................................................ Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)............................................................................................ Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... Figure 14.
Figure 14.31 Timing for Fixing Clock Output Level................................................................... Figure 14.32 Clock Halt and Restart Procedure .......................................................................... Figure 14.33 Block Diagram of IrDA.......................................................................................... Figure 14.34 IrDA Transmit/Receive Operations........................................................................ Figure 14.
Section 17 D/A Converter Figure 17.1 Block Diagram of D/A Converter .......................................................................... 682 Figure 17.2 Example of D/A Converter Operation.................................................................... 686 Section 19 Flash Memory (0.35-μm F-ZTAT Version) Figure 19.1 Block Diagram of Flash Memory........................................................................... Figure 19.2 Flash Memory State Transitions......................................
Section 21 Mask ROM Figure 21.1 Block Diagram of 256-kbyte Mask ROM (HD6432365)....................................... 811 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Figure 22.6 Figure 22.7 Clock Pulse Generator Block Diagram of Clock Pulse Generator .............................................................. Connection of Crystal Oscillator (Example) .......................................................... Crystal Oscillator Equivalent Circuit .............................
Figure 25.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1).............. Figure 25.22 External Bus Release Timing ................................................................................. Figure 25.23 External Bus Request Output Timing..................................................................... Figure 25.24 DMAC Single Address Transfer Timing: Two-State Access................................. Figure 25.25 DMAC Single Address Transfer Timing: Three-State Access...........
Tables Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode ............................................................ 8 Table 1.2 Pin Functions.......................................................................................................... 14 Section 2 CPU Table 2.1 Instruction Classification........................................................................................ Table 2.2 Operation Notation .........................................................................
Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration ................................................................................................... 121 Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ........................................ 147 Table 6.3 Data Buses Used and Valid Strobes ....................................................................... 152 Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. 165 Table 6.
Table 9.6 MOS Input Pull-Up States (Port E) ........................................................................ 388 Section 10 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Table 10.15 Table 10.16 Table 10.17 Table 10.18 Table 10.19 Table 10.20 Table 10.21 Table 10.22 Table 10.23 Table 10.24 Table 10.25 Table 10.26 Table 10.27 Table 10.28 Table 10.29 Table 10.30 Table 10.31 Table 10.
Section 11 Programmable Pulse Generator (PPG) Table 11.1 Pin Configuration ................................................................................................... 487 Section 12 8-Bit Timers (TMR) Table 12.1 Pin Configuration ................................................................................................... Table 12.2 Clock Input to TCNT and Count Condition ........................................................... Table 12.3 8-Bit Timer Interrupt Sources ......................
Table 16.2 Table 16.3 Table 16.4 Table 16.5 Table 16.6 Analog Input Channels and Corresponding ADDR Registers................................ A/D Conversion Time (Single Mode) .................................................................... A/D Conversion Time (Scan Mode)....................................................................... A/D Converter Interrupt Source ............................................................................. Analog Pin Specifications ............................
Section 22 Clock Pulse Generator Table 22.1 Damping Resistance Value .................................................................................... 816 Table 22.2 Crystal Oscillator Characteristics ........................................................................... 817 Table 22.3 External Clock Input Conditions............................................................................ 818 Section 23 Power-Down Modes Table 23.1 Operating Modes and Internal States of the LSI ...................
Table 25.30 Table 25.31 Table 25.32 Table 25.33 Table 25.34 Table 25.35 Table 25.36 Table 25.37 Table 25.38 Clock Timing.......................................................................................................... Control Signal Timing............................................................................................ Bus Timing (1) ....................................................................................................... Bus Timing (2) ....................................
Rev.6.00 Mar.
Section 1 Overview Section 1 Overview 1.
Section 1 Overview • On-chip memory ROM Type Model ROM RAM Remarks Flash memory version HD64F2368F 512 kbytes 32 kbytes H8S/2368 0.18 μm F-ZTAT Group HD64F2367F 384 kbytes 24 kbytes HD64F2364 384 kbytes 32 kbytes H8S/2368 0.18 μm F-ZTAT Group HD64F2362F 256 kbytes 32 kbytes H8S/2368 0.18 μm F-ZTAT Group HD64F2361 256 kbytes 24 kbytes H8S/2368 0.18 μm F-ZTAT Group HD64F2360 256 kbytes 16 kbytes H8S/2368 0.
Section 1 Overview 1.
Port 8 PC7/A7 PC6/A6 PC5/A5 PC4/A4 PC3/A3 PC2/A2 PC1/A1 PC0/A0 P35/SCK1/SCL0/(OE) P34/SCK0/SCK4/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD WDT RAM SCI × 5 channels I2C bus interface 2 (option) P85/SCK3 P83/RxD3 P81/TxD3 Port A DMAC ROM (Flash memory) Port B Port F DTC PB7/A15 PB6/A14 PB5/A13 PB4/A12 PB3/A11 PB2/A10 PB1/A9 PB0/A8 Port C PG6/BREQ PG5/BACK PG4/CS4/BREQO PG3/CS3/RAS3 PG2/CS2/RAS2 PG1/CS1 PG0/CS0 Interrupt controller Port G PF7/φ PF6/AS PF5/RD PF4/HWR PF3/LWR
Section 1 Overview 1.3 Pin Description 1.3.1 Pin Arrangement 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PG1/CS1 PG0/CS0 STBY VSS P81/TxD3 P83/RxD3 VCC VCC EXTAL XTAL VSS PF7/φ PLLVSS RES PLLVCC PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/CS6/LCAS PF1/CS5/UCAS PF0/WAIT/OE PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Figures 1.3 to 1.5 show the pin arrangements of this LSI.
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PG1/CS1 PG0/CS0 STBY VSS P81/TxD3 P83/RxD3 VCC VCC EXTAL XTAL VSS PF7/φ PLLVSS RES PLLVCC PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/CS6/LCAS PF1/CS5/UCAS PF0/WAIT/OE PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8 Section 1 Overview 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 TFP-120 (Top view) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
FP-128B (Top view) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VSS PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 P85/SCK3 P27/PO7/TIOCB5 P26/PO6/TIOCA5 P25/PO5/TIOCB4/TMO1 P24/PO4/TIOCA4/TMO0/RxD4 P23/PO3/TIOCD3/TMCI1/TxD4 P22/PO2/TIOCC3/TMCI0 P21/PO1/TIOCB3/TMR
Section 1 Overview 1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No. Pin Name Mode 7 TFP-120 QFP-128*1 Mode 1 Mode 2 Mode 4 EXPE = 1 EXPE = 0 Flash Memory Programmer Mode ⎯ 3 Vss Vss Vss Vss Vss Vss ⎯ 4 Vss Vss Vss Vss Vss Vss Notes: 1. Not supported by the H8S/2368 0.18 μm F-ZTAT Group. 2. Used as the VCL pin in the H8S/2368 0.18 μm F-ZTAT Group. Rev.6.00 Mar.
Section 1 Overview 1.3.3 Pin Functions Table 1.2 Pin Functions Pin No. Type Symbol Function 2, 33* , 60, 6,39,66, 83, 84 91,92 Input Power supply pins. VCC pins should be connected to the system power supply. Vss 8, 17, 22, 58, 80, 87 3,4,12,21, 26,35,36, 64,68,88, 95,99,100 Input Ground pins. VSS pins should be connected to the system power supply (0 V). PLLVCC 76 84 Input Power supply pin for the on-chip PLL oscillator. PLLVSS 78 86 Input Ground pin for the on-chip PLL oscillator.
Section 1 Overview Pin No. 1 TFP-120 QFP-128* I/O Function 77 85 Input Reset pin. When this pin is driven low, the chip is reset. STBY 88 96 Input When this pin is driven low, a transition is made to hardware standby mode. EMLE 30 34 Input Enables emulator. This pin should be connected to the power supply (0 V). Address bus A23 to A0 29 to 23, 21 to 18, 16 to 9, 7 to 3 33 to 27, 25 to 22, 20 to 13, 11 to 7 Output Address output pins.
Section 1 Overview Pin No. 1 Type Symbol TFP-120 QFP-128* I/O Bus control BACK 107 117 Output Indicates the bus is released to the external bus master. UCAS 70 78 Output Upper column address strobe signal for accessing the 16-bit DRAM space. Function Column address strobe signal for accessing the 8-bit DRAM space. LCAS 71 79 Output Lower column address strobe signal for accessing the 16-bit DRAM space. RAS2 RAS3 91 92 101 102 Output Row address strobe signal for the DRAM interface.
Section 1 Overview Pin No. 1 TFP-120 QFP-128* I/O Function 41, 39, 37, 36 47, 45, 43, 42 Input External clock input pins for the timer. TIOCA0 TIOCB0 TIOCC0 TIOCD0 34, 35, 36, 37 40, 41, 42, 43 Input/ output TGRA_0 to TGRD_0 input capture input/output compare output/PWM output pins. TIOCA1 TIOCB1 38, 39 44, 45 Input/ output TGRA_1 and TGRB_1 input capture input/output compare output/PWM output pins.
Section 1 Overview Pin No. 1 TFP-120 QFP-128* I/O 45, 86, 109, 117, 118 51, 94, 119, 127, 128 Output Data output pins. 46, 85, 110, 115, 116 52, 93, 120 125, 126 Input Data input pins. SCK4 SCK3 SCK2 SCK1 SCK0 114, 50, 111, 113, 114 124, 56, 121, 123, 124 Input/ output Clock input/output pins. IIC bus SCL1 interface2 (IIC2) SCL0 115, 113 125, 123 Input/ output IIC clock input/output pins. SDA1 SDA0 116, 114 126, 124 Input/ output IIC data input/output pins.
Section 1 Overview Pin No. 1 Type Symbol TFP-120 QFP-128* I/O Function A/D converter, D/A converter Vref 94 104 Input The reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). I/O ports P17 to P1041 to 34 47 to 40 Input/ output Eight-bit input/output pins. P27 to P2049 to 42 55 to 48 Input/ output Eight-bit input/output pins.
Section 1 Overview Pin No. 1 QFP-128* Type Symbol TFP-120 I/O ports PG6 to PG0 108 to 106, 118 to 116, 92 to 89 102,101, 98,97 I/O Function Input/ Seven-bit input/output pins. output Notes: 1. Not supported by the H8S/2368 0.18 μm F-ZTAT Group. 2. VCL on the H8S/2368 0.18 µm F-ZTAT Group. Do not connect to VCL. 3. H8S/2368 0.18 µm F-ZTAT Group only. Rev.6.00 Mar.
Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
Section 2 CPU ⎯ 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) ⎯ 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W) • Two CPU operating modes ⎯ Normal mode* ⎯ Advanced mode Note: * For this LSI, normal mode is not available. • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Section 2 CPU 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space ⎯ Normal mode supports the same 64-kbyte address space as the H8/300 CPU. ⎯ Advanced mode supports a maximum 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. • Address space Linear access to a maximum address space of 64 kbytes is possible.
Section 2 CPU Note: For this LSI, normal mode is not available. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP (SP *2 Reserved*1*3 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1.
Section 2 CPU 2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. • Instruction set All instructions and addressing modes can be used.
Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
Section 2 CPU 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended control register (EXR), and an 8-bit condition code register (CCR).
Section 2 CPU 2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC instructions.
Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. Rev.6.00 Mar.
Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller. 6 UI Undefined R/W User Bit or Interrupt Mask Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions.
Section 2 CPU 2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. Note that the stack pointer (ER7) is undefined. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 2.
Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB Legend: ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2.9 General Register Data Formats (2) Rev.6.00 Mar.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.
Section 2 CPU 2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Section 2 CPU Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.
Section 2 CPU Table 2.4 Arithmetic Operations Instructions Instruction Size*1 Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd SUB ADDX Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.
Section 2 CPU Instruction Size*1 Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.
Section 2 CPU Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.7 Bit Manipulation Instructions Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ∼ (
Section 2 CPU Instruction Size* Function BXOR B C ⊕ ( of ) → C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼ ( of ) → C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc – Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.9 System Control Instructions Instruction Size* Function TRAPA – Starts trap-instruction exception handling. RTE – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B – if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: EEPMOV.W – if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.
Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) Rev.6.00 Mar.
Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
Section 2 CPU 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.
Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address 2.7.
Section 2 CPU Note that the top area of the address range in which the branch address is stored is also used for the exception vector area. For further details, refer to section 4, Exception Handling. If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or the instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.
Section 2 CPU Table 2.13 Effective Address Calculation No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
Section 2 CPU Addressing Mode and Instruction Format No 5 Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
Section 2 CPU 2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
Section 2 CPU End of bus request Bus request ep tio n ha ex nd ce lin pt g ion ha nd lin g En d of st fo r d ue En Re q Exception handling state Sleep mode st que t re rrup Inte n ex c Bus-released state =0 BY SS EEP tion SL truc ins io = 1 ruct BY nst SS EP i E SL of bu s re Bu qu sr es eq t ue st Program execution state External interrupt request Software standby mode RES = High Reset STBY = High, RES = Low state*1 Reset state Hardware standby mode*2 Power down state*3 Notes:
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI has six operating modes (modes 1 to 5 and 7). Modes 1 to 5 and 7 are available in the H8S/2368 0.18 μm F-ZTAT Group flash memory version. Modes 1 to 4 and 7 are available in the H8S/2367F. Modes 1, 2, 4, and 7 are available in the masked ROM version. Modes 1 and 2 are available in the ROMless version. The operating mode is selected by the setting of mode pins (MD2 to MD0).
Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this LSI. Bit 7 to 3 2 1 0 Note: 3.2.2 Bit Name Initial Value R/W − All 0 − MDS2 MDS1 MDS0 −* −* −* R R R * Descriptions Reserved These bits are always read as 0 and cannot be modified.
Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Descriptions 7, 6 − All 1 R/W R/W Reserved The initial value should not be modified. 5, 4 − All 0 R/W R/W Reserved The initial value should not be modified. 3 FLSHE 0 R/W Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). If this bit is set to 1, the flash memory control registers can be read/written to.
Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of ports F, and G, carry bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access is designated for all areas by the bus controller, the bus mode switches to 8 bits. 3.3.
Section 3 MCU Operating Modes In the flash memory version, user program mode is entered by setting the SWE bit of FLMCR1 to 1. 3.3.5 Mode 5 This mode is a user boot mode of the flash memory. This mode is the same as mode 7, except for the programming and erasure on the flash memory. Mode 5 is only available in the H8S/2368 0.18 μm F-ZTAT Group. 3.3.6 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, and the chip starts up in single-chip mode.
Section 3 MCU Operating Modes 3.3.7 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.
Section 3 MCU Operating Modes 3.4 Memory Map in Each Operating Mode Figures 3.1 to 3.15 show memory maps for each product.
Section 3 MCU Operating Modes ROM: 512 kbytes RAM: 32 kbytes Mode 5 (User boot mode) ROM: 512 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'080000 H'080000 H'FF4000 H'FF4000 On-chip RAM/ external address space*1 External address space/ reserved area*2*4 H'FF4000 On-chip RAM/ external address space *3 On-chip RAM *5 H'FFC000 Reserved area*4 H'FFD000 External address space H'FFFF20 H'FFFFFF On-chip ROM External address space/ reserved area*
Section 3 MCU Operating Modes ROM: 384 kbytes RAM: 24 kbytes Mode 3 (Boot mode) RAM: 24 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 H'000000 On-chip ROM External address space H'060000 External address space/ reserved area*2*4 H'FF4000 H'FF6000 H'FFC000 H'FF4000 H'FF6000 Reserved area*4 On-chip RAM*3 H'FFC000 Reserved area*4 H'FFC800 External address space H'FFC800 External address space/ reserved area*2*4 H'FFFC00 Internal I/O registers H'FFFC00 Internal I/O
Section 3 MCU Operating Modes ROM: 384 kbytes RAM: 24 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) ROM: 384 kbytes RAM: 24 kbytes Mode 7 (Single-chip activation expanded mode, with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'060000 On-chip ROM H'060000 External address space/ reserved area*2*4 External address space H'FF4000 H'FF6000 H'FFC000 Reserved area On-chip RAM/ external address space*1 Reserved area H'FF4000 H'FF6000 H'FFC000 Reserved area*4 On-chip RAM/ external ad
Section 3 MCU Operating Modes RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 ROM: 384 kbytes RAM: 32 kbytes Mode 3 (Boot mode) H'000000 On-chip ROM H'060000 Reserved area*4 External address space H'080000 External address space/ reserved area*2*4 H'FF4000 H'FF4000 On-chip RAM/ external address space*1 H'FFC000 Reserved area*4 On-chip RAM*3 H'FFC000 Reserved area*4 External address space/ reserved area*2*4 H'FFD000 External address space H'FFD000 H'FFFC00 Inte
Section 3 MCU Operating Modes ROM: 384 kbytes RAM: 32 kbytes Mode 5 (User boot mode) ROM: 384 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'060000 H'080000 H'060000 H'080000 Reserved area*4 H'080000 External address space/ reserved area*2*4 External address space H'FF4000 H'FF4000 On-chip RAM/ external address space*1 External address space/ reserved area*2*4 H'FF4000 On-chip RAM/ external address space*3 On-chip RAM *5 H'FFC000 Reser
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 32 kbytes Mode 3 (Boot mode) RAM: 32 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 H'000000 On-chip ROM H'040000 Reserved area*4 External address space H'080000 External address space/ reserved area*2*4 H'FF4000 H'FF4000 On-chip RAM/ external address space*1 H'FFC000 Reserved area*4 On-chip RAM*3 H'FFC000 Reserved area*4 H'FFD000 External address space H'FFD000 External address space/ reserved area*2*4 H'FFFC00 In
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 32 kbytes Mode 5 (User boot mode) ROM: 256 kbytes RAM: 32 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'040000 H'060000 H'040000 H'060000 Reserved area*4 H'060000 External address space/ reserved area*2*4 External address space H'FF4000 H'FF4000 On-chip RAM/ external address space*1 External address space/ reserved area*2*4 H'FF4000 On-chip RAM/ external address space *3 On-chip RAM *5 H'FFC000 Reser
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 24 kbytes Mode 3 (Boot mode) RAM: 24 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 H'000000 On-chip ROM H'040000 Reserved area*4 External address space H'080000 External address space/ reserved area*2*4 H'FF4000 Reserved area*4 H'FF6000 H'FF4000 On-chip RAM/ external address space*1 H'FFC000 Reserved area*4 H'FF6000 Reserved area*4 On-chip RAM*3 H'FFC000 Reserved area*4 H'FFD000 External address space H'FFD000 H
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 24 kbytes Mode 5 (User boot mode) ROM: 256 kbytes RAM: 24 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'040000 H'080000 Reserved area*4 H'FF4000 On-chip RAM/ external address space*1 Reserved area*4 H'FFD000 External address space H'FFFF20 H'FFFFFF H'080000 Reserved area*4 H'FF6000 H'FFC000 Internal I/O registers External address space Internal I/O registers Reserved area*4 External address space/ re
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 16 kbytes Mode 3 (Boot mode) RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 H'000000 On-chip ROM H'040000 Reserved area*4 External address space H'080000 External address space H'FF4000 Reserved area*4 H'FF8000 H'FF4000 On-chip RAM/ external address space*1 H'FFC000 Reserved area*4 H'FF8000 Reserved area*4 On-chip RAM*3 H'FFC000 Reserved area*4 H'FFD000 External address space H'FFD000 External address spa
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 16 kbytes Mode 5 (User boot mode) ROM: 256 kbytes RAM: 16 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'040000 H'080000 Reserved area*4 H'FF4000 On-chip RAM/ external address space*1 Reserved area*4 H'FFD000 External address space H'FFFF20 H'FFFFFF H'080000 Reserved area*4 H'FF8000 H'FFC000 Internal I/O registers External address space Internal I/O registers Reserved area*4 External address space/ re
Section 3 MCU Operating Modes ROM: 256 kbytes RAM: 16 kbytes Mode 4 (Expanded mode with on-chip ROM enabled) RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 H'000000 On-chip ROM H'040000 External address space Reserved area*2 H'060000 External address space H'FF4000 H'FF8000 H'FFC000 Reserved area*2 On-chip RAM/ external address space*1 Reserved area*2 H'FF4000 H'FF8000 H'FFC000 Reserved area*2 On-chip RAM/ external address space*1 Reserved area*2 H'FFC800 Exte
Section 3 MCU Operating Modes ROM: 258 kbytes RAM: 16 kbytes Mode 7 (Single-chip activation expanded mode, with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area*3 H'060000 External address space/ reserved area*1*3 H'FF4000 H'FF8000 Reserved area*3 On-chip RAM/ external address space*2 H'FFC000 H'FFC800 Reserved area*3 External address space/ reserved area*1*3 H'FFFC00 Internal I/O registers H'FFFF00 External address space/ reserved area*1*3 H'FFFF20 Internal I/O registers H'FFFFFF
Section 3 MCU Operating Modes RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF8000 H'FFC000 On-chip RAM/ external address space*1 Reserved area*2 H'FFC800 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF Internal I/O registers Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0. 2. Do not access a reserved area. Figure 3.
Section 3 MCU Operating Modes Rev.6.00 Mar.
Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode.
Section 4 Exception Handling Table 4.
Section 4 Exception Handling Vector Address*1 Exception Source Vector Number Normal Mode*2 Advanced Mode Reserved for system use 30 H'003C to H'003D H'0078 to H'007B 31 H'003E to H'003F H'007C to H'007F 32 ⎜ 118 H'0040 to H'0041 ⎜ H'00EC to H'00ED H'0080 to H'0083 ⎜ H'01D8 to H'01DB Internal interrupt*4 Notes: 1. 2. 3. 4. 4.3 Lower 16 bits of the address. Not available in this LSI. Not available in this LSI. It is reserved for system use.
Section 4 Exception Handling Vector fetch Prefetch of first Internal processing program instruction (1) (3) φ Internal address bus (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.
Section 4 Exception Handling Internal processing Vector fetch * Address bus * (1) * (3) (5) High , D15 to D0 Prefetch of first program instruction (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted. Figure 4.
Section 4 Exception Handling Consequently, on-chip peripheral module registers cannot be read from or written to. Register reading and writing is enabled when module stop mode is exited. 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated.
Section 4 Exception Handling 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. A vector address corresponding to the interrupt source is generated, the start address is loaded from the vector table to the PC, and program execution starts from that address. 4.6 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state.
Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Notes: 1. Ignored on return. 2.
Section 4 Exception Handling 4.8 Usage Notes When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.
Section 4 Exception Handling Rev.6.00 Mar.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times.
Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1.
Section 5 Interrupt Controller 5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected. IRQ7 to IRQ0 Input Maskable external interrupts Rising edge, falling edge, both edges, or level sensing, can be selected. 5.3 Register Descriptions The interrupt controller has the following registers.
Section 5 Interrupt Controller 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W Description 7, 6 − All 0 − Reserved These bits are always read as 0 and cannot be modified. 5 4 INTM1 INTM0 0 0 R/W R/W Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit.
Section 5 Interrupt Controller 5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding interrupt. IPR should be read in word size.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 6 5 4 IPR6 IPR5 IPR4 1 1 1 R/W R/W R/W Sets the priority of the corresponding interrupt source. 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (Highest) 3 − 0 − 2 1 0 IPR2 IPR1 IPR0 1 1 1 R/W R/W R/W Reserved This bit is always read as 0 and cannot be modified.
Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Bit Name Initial Value R/W Description 15 to 8 − All 0 R/W Reserved 7 IRQ7E The write value should always be 0. 0 R/W IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1. 6 IRQ6E 0 R/W IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1.
Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Register L (ISCRL) ISCRL select the source that generates an interrupt request at pins IRQ7 to IRQ0.
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 8 IRQ4SCB IRQ4SCA 0 0 R/W R/W IRQ4 Sense Control B IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 6 IRQ3SCB IRQ3SCA 0 0 R/W R/W IRQ3 Sense Control B IRQ3 Sense Control A 00: Interrupt requ
Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 2 IRQ1SCB IRQ1SCA 0 0 R/W R/W IRQ1 Sense Control B IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 0 IRQ0SCB IRQ0SCA 0 0 R/W R/W IRQ0 Sense Control B IRQ0 Sense Control A 00: Interrupt requ
Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ7 to IRQ0 interrupt request flag register. Bit Bit Name Initial Value R/W Description 15 to 8 − All 0 R/W Reserved 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* The write value should always be 0.
Section 5 Interrupt Controller 5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ7 to IRQ0. Bit Bit Name Initial Value R/W Description 15 to 8 − All 0 R/W Reserved The write value should always be 0. 7 ITS7 0 R/W Selects IRQ7 input pin. 0: PA7 1: P47 6 ITS6 0 R/W Selects IRQ6 input pin. 0: PA6 1: P46 5 ITS5 0 R/W Selects IRQ5 input pin. 0: PA5 1: P45 4 ITS4 0 R/W Selects IRQ4 input pin. 0: PA4 1: P44 3 ITS3 0 R/W Selects IRQ3 input pin.
Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value R/W Description 15 to 8 — All 0 R/W Reserved The write value should always be 0. 7 6 5 4 3 2 1 0 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 0 0 0 0 0 0 0 0 5.4 Interrupt Sources 5.4.
Section 5 Interrupt Controller When IRQ7 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in the interrupt handling routine and clear the IRQnF bit (n = 0 to 7) in ISR to 0. Interrupts may not be executed when the corresponding IRQ is set to high before the interrupt handling starts.
Section 5 Interrupt Controller 5.5 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Table 5.
Section 5 Interrupt Controller Vector Address* Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC DMAC Activation Activation Refresh controller CMI 35 H'008C IPRE2 to IPRE0 High — — — Reserved for system use 36 H'0090 IPRF14 to IPRF12 — — 37 H'0094 — — A/D ADI 38 H'0098 O O — Reserved for system use 39 H'009C — — TPU_0 TGI0A 40 H'00A0 O O TGI0B 41 H'00A4 O — TGI0C 42 H'00A8 O — TGI0D 43 H'00AC O — TCI0V 44 H'00B0 — — Reserv
Section 5 Interrupt Controller Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC DMAC Activation Activation TPU_4 TGI4A 64 H'0100 IPRG6 to IPRG4 High O O TGI4B 65 H'0104 O — TCI4V 66 H'0108 — — TCI4U 67 H'010C — — TGI5A 68 H'0110 O O TGI5B 69 H'0114 O — — TPU_5 IPRG2 to IPRG0 TCI5V 70 H'0118 — TCI5U 71 H'011C — — CMIA0 72 H'0120 O — CMIB0 73 H'0124 O — OVI0 74 H'0128 — — — Reserved for
Section 5 Interrupt Controller Vector Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC DMAC Activation Activation SCI_1 ERI1 92 H'0170 IPRJ14 to IPRJ12 High — — RXI1 93 H'0174 O O TXI1 94 H'0178 O O TEI1 95 H'017C — — ERI2 96 H'0180 — — RXI2 97 H'0184 O — — SCI_2 SCI_3 SCI_4 — — IIC2 IPRJ10 to IPRJ8 TXI2 98 H'0188 O TEI2 99 H'018C — — ERI3 100 H'0190 — — RXI3 101 H'0194 — — TXI3 102 H'0198
Section 5 Interrupt Controller Interrupt Source — Origin of Interrupt Source Reserved for system use Vector Address* Vector Number Advanced Mode IPR Priority DTC DMAC Activation Activation 120 H'01E0 IPRK2 to IPRK0 High — — 121 H'01E4 — — 122 H'01E8 — — 123 H'01EC — — 124 H'01F0 — — 125 H'01F4 — — 126 H'01F8 127 Note: * H'01EC Low — — — — Lower 16 bits of the start address. Rev.6.00 Mar.
Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.
Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. Program execution status No Interrupt generated? Yes Yes NMI No I=0 No Hold pending Yes No IRQ0 Yes No IRQ1 Yes IICI1 Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.
Section 5 Interrupt Controller 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2.
Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes No Level 6 interrupt? No Yes Level 1 interrupt? No Mask level 5 or below? No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.6.00 Mar.
Section 5 Interrupt Controller 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev.6.00 Mar.
(1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed.
Section 5 Interrupt Controller 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.
Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8-Bit Bus 16-Bit Bus Symbol Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch SI 1 4 6+2m 2 3+m Branch address read SJ Stack manipulation SK Legend: m: Number of wait states in an external device access. 5.6.5 DTC and DMAC Activation by Interrupt The DTC and DMAC can be activated by an interrupt.
Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction.
Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.
Section 5 Interrupt Controller 5.7.6 Note on IRQ Status Register (ISR) Since IRQnF flags may be set to 1 depending on the pin states after a reset, be sure to read from ISR after a reset and then write 0 to clear the IRQnF flags. Rev.6.00 Mar.
Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus masters—the CPU, DMA controller (DMAC) and data transfer controller (DTC). 6.
Section 6 Bus Controller (BSC) A block diagram of the bus controller is shown in figure 6.1.
Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Read RD Output Strobe signal indicating that normal space is being read.
Section 6 Bus Controller (BSC) Name Symbol I/O Function Lower column address strobe LCAS Output 16-bit DRAM space lower column address strobe signal. Output enable OE Output Output enable signal for the DRAM space. Wait WAIT Input Wait request signal when accessing external address space. Bus request BREQ Input Request signal for release of bus to external bus master. Bus request acknowledge BACK Output Acknowledge signal indicating that bus has been released to external bus master.
Section 6 Bus Controller (BSC) • Refresh control register (REFCR) • Refresh timer counter (RTCNT) • Refresh time constant register (RTCOR) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value* R/W Description 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 R/W R/W R/W R/W R/W R/W R/W R/W Area 7 to 0 Bus Width Control Note: 6.3.
Section 6 Bus Controller (BSC) 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. • WTCRAH Bit Bit Name Initial Value R/W 15 − 0 R Description Reserved This bit is always read as 0 and cannot be modified.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 9 8 W62 W61 W60 1 1 1 R/W R/W R/W Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 3 − 0 R Reserved This bit is always read as 0 and cannot be modified. 2 1 0 W42 W41 W40 1 1 1 R/W R/W R/W Area 4 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1.
Section 6 Bus Controller (BSC) • WTCRBH Bit Bit Name Initial Value R/W Description 15 − 0 R Reserved This bit is always read as 0 and cannot be modified. 14 13 12 W32 W31 W30 1 1 1 R/W R/W R/W Area 3 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1.
Section 6 Bus Controller (BSC) • WTCRBL Bit Bit Name Initial Value R/W 7 − 0 R Description Reserved This bit is always read as 0 and cannot be modified. 6 5 4 W12 W11 W10 1 1 1 R/W R/W R/W Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1.
Section 6 Bus Controller (BSC) 6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access. As shown in figure 6.
Section 6 Bus Controller (BSC) 6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL) CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices.
Section 6 Bus Controller (BSC) Bus cycle Th T1 T2 T3 Tt φ Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit Bit Name Initial Value R/W 7 BSRMn 0 R/W Description Burst ROM Interface Select Selects the basic bus interface or burst ROM interface.
Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W Description 15 BRLE 0 R/W External Bus Release Enable Enables or disables external bus release.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ICIS0 1 R/W Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle.
Section 6 Bus Controller (BSC) 6.3.8 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM interface settings. Bit Bit Name Initial Value R/W Description 15 OEE 0 R/W OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin. The OE signal is common to all areas designated as DRAM space.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 9 8 RMTS2 RMTS1 RMTS0 0 0 0 R/W R/W R/W DRAM Space Select These bits designate DRAM space for areas 2 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 6 RCDM 0 R/W RAS Down Mode When access to DRAM space is interrupted by an access to normal space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode). The setting of this bit is valid only when the BE bit is set to 1.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 1 0 MXC2 MXC1 MXC0 0 0 0 R/W R/W R/W Address Multiplex Select These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM interface, these bits also select the row address bits to be used for comparison. For details, refer to section 6.6.2, Address Multiplexing.
Section 6 Bus Controller (BSC) Bus cycle Tp Tr Tc1 Tc2 φ Row address Address Column address RAST = 0 RAS RAST = 1 RAS UCAS, LCAS Figure 6.4 RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) 6.3.9 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM interface bus specifications. Bit Bit Name Initial Value R/W Description 7 DRMI 0 R/W Idle Cycle Insertion An idle cycle can be inserted after a DRAM access cycle when a continuous normal space access cycle follows a DRAM access cycle. Idle cycle insertion conditions, setting of number of states, etc.
Section 6 Bus Controller (BSC) 6.3.10 Refresh Control Register (REFCR) REFCR specifies DRAM interface refresh control. Bit 15 Bit Name CMF Initial Value R/W Description 0 R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 9 8 RTCK2 RTCK1 RTCK0 0 0 0 R/W R/W R/W Refresh Counter Clock Select These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up.
Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 3 SLFRF 0 R/W Self-Refresh Enable If this bit is set to 1, DRAM self-refresh mode is selected when a transition is made to the software standby state. This bit is valid when the RFSHE bit is set to 1, enabling refresh operations. It is cleared after recovery from software standby mode.
Section 6 Bus Controller (BSC) 6.3.11 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match interrupt (CMI) is generated.
Section 6 Bus Controller (BSC) H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7 (2 Mbytes) H'FFFFFF Figure 6.5 Area Divisions Rev.6.00 Mar.
Section 6 Bus Controller (BSC) 6.4.2 Bus Specifications The external space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
Section 6 Bus Controller (BSC) Table 6.
Section 6 Bus Controller (BSC) 6.4.3 Memory Interfaces The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on a synchronous DRAM interface that allows direct connection of synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area.
Section 6 Bus Controller (BSC) Only the basic bus interface can be used for area 6. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external space. The onchip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in external space.
Section 6 Bus Controller (BSC) Bus cycle T1 Address bus T2 T3 Area n external address Figure 6.6 CSn Signal Output Timing (n = 0 to 7) 6.5 Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Section 6 Bus Controller (BSC) Upper data bus D15 Lower data bus D8 D7 D0 Byte size Word size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit Access Space: Figure 6.8 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses.
Section 6 Bus Controller (BSC) 6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
Section 6 Bus Controller (BSC) 6.5.3 Basic Timing 8-Bit, 2-State Access Space: Figure 6.9 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.
Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.
Section 6 Bus Controller (BSC) 16-Bit, 2-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted. Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2.
Section 6 Bus Controller (BSC) Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space: Figures 6.14 to 6.16 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) 6.5.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings in WTCRA and WTCRB.
Section 6 Bus Controller (BSC) By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDN = 0 Figure 6.17 Example of Wait State Insertion Timing 6.5.5 Read Strobe (RD) Timing The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.
Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus DACK Figure 6.18 Example of Read Strobe Timing 6.5.6 Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR.
Section 6 Bus Controller (BSC) Bus cycle Th T1 T2 T3 Tt φ Address bus CSn AS Read (when RDNn = 0) RD Data bus Read data HWR, LWR Write Data bus Write data Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas.
Section 6 Bus Controller (BSC) 6.6 DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode. 6.6.1 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR.
Section 6 Bus Controller (BSC) Table 6.
Section 6 Bus Controller (BSC) 6.6.4 Pins Used for DRAM Interface Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2, CS5 pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2, RAS5 signals are output. Table 6.
Section 6 Bus Controller (BSC) 6.6.5 Basic Timing Figure 6.20 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2, 3 Figure 6.
Section 6 Bus Controller (BSC) from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space, the signal is output only from the RD pin. 6.6.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.
Section 6 Bus Controller (BSC) 6.6.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.22 shows an example of the timing when the RAS signal goes low from the beginning of the Tr state.
Section 6 Bus Controller (BSC) If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output.
Section 6 Bus Controller (BSC) 6.6.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.24 shows the timing when two Tp states are inserted.
Section 6 Bus Controller (BSC) 6.6.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access.
Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Notes: Downward arrows indicate the timing of WAIT pin sampling. n = 2, 3 Figure 6.25 Example of Wait State Insertion Timing (2-State Column Address Output) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) Tp Tr By program wait By WAIT pin Tc1 Tw Tw Tc2 Tc3 φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Notes: Downward arrows indicate the timing of WAIT pin sampling. n = 2, 3 Figure 6.26 Example of Wait State Insertion Timing (3-State Column Address Output) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) 6.6.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.27 shows the control timing for 2-CAS access, and figure 6.28 shows an example of 2-CAS DRAM connection. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS LCAS High WE (HWR) OE (RD) High Upper data bus Write data High impedance Lower data bus Note: n = 2, 3 Figure 6.
Section 6 Bus Controller (BSC) This LSI (Address shift size set to 10 bits) 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration 10-bit column address RASn (CSn) RAS UCAS UCAS LCAS LCAS HWR (WE) RD (OE) A10 WE OE A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 Figure 6.28 Example of 2-CAS DRAM Connection 6.6.
Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc1 Tc2 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2, 3 Figure 6.29 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2, 3 Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details see section 6.6.
Section 6 Bus Controller (BSC) ⎯ the chip enters software standby mode ⎯ the external bus is released ⎯ the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction.
Section 6 Bus Controller (BSC) • RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.32 shows an example of the timing in RAS up mode.
Section 6 Bus Controller (BSC) 6.6.12 Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in REFCR.
Section 6 Bus Controller (BSC) RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.34 Compare Match Timing TRp TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Note: n = 2, 3 Figure 6.35 CBR Refresh Timing A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations. Figure 6.
Section 6 Bus Controller (BSC) TRp TRrw TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Note: n = 2, 3 Figure 6.36 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) Depending on the DRAM used, modification of the WE signal may not be permitted during the refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.37 shows an example of the timing when the CBRM bit is set to 1.
Section 6 Bus Controller (BSC) Normal space access request φ A23 to A0 CS AS RD HWR (WE) Refresh period RAS CAS Figure 6.37 Example of CBR Refresh Timing (CBRM = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR.
Section 6 Bus Controller (BSC) TRp Software standby TRr TRc3 φ CSn (RASn) UCAS, LCAS HWR (WE) High Note: n = 2, 3 Figure 6.38 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time.
Section 6 Bus Controller (BSC) Software standby DRAM space write Trc3 Trp1 Trp2 Tp Tr Tc1 Tc2 φ Address bus RASn (CSn) UCAS, LCAS OE (RD) HWR (WE) Data bus Note: n = 2, 3 Figure 6.
Section 6 Bus Controller (BSC) When DDS = 1 : Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the DACK output goes low from the Tc1 state. Figure 6.40 shows the DACK output timing for the DRAM interface when DDS = 1. Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus DACK Note: n = 2, 3 Figure 6.
Section 6 Bus Controller (BSC) When DDS = 0 : When DRAM space is accessed in DMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK output goes low from the Tr state. In modes other than DMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.41 shows the DACK output timing for the DRAM interface when DDS = 0.
Section 6 Bus Controller (BSC) 6.7 Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Continuous burst accesses of 4, 8, 16, or 32 words can be performed, according to the setting of the BSWD11 and BSWD10 bits in BROMCR.
Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1, 0 Figure 6.42 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev.6.00 Mar.
Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1, 0 Figure 6.43 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.7.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control. Wait states cannot be inserted in a burst cycle.
Section 6 Bus Controller (BSC) 6.8 Idle Cycle 6.8.1 Operation When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR.
Section 6 Bus Controller (BSC) Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.45 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Section 6 Bus Controller (BSC) Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T2 T1 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD HWR, LWR HWR Data bus Data bus Long output floating time (a) No idle cycle insertion (ICIS2 = 0) Data collision T2 T3 Bus cycle B Ti T1 T2 Idle cycle (b) Idle cycle insertion (ICIS2 = 1, initial value) Figure 6.
Section 6 Bus Controller (BSC) Bus cycle A T1 T2 T3 Bus cycle B T1 Bus cycle A T2 T1 φ φ Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) RD RD T2 Bus cycle B T3 Overlap period between CS (area B) and RD may occur Ti T1 T2 Idle cycle (b) Idle cycle insertion (ICIS1 = 1, initial value) (a) No idle cycle insertion (ICIS1 = 0) Figure 6.
Section 6 Bus Controller (BSC) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 6.49 and 6.50. DRAM space read Tp Tr Tc1 External read Tc2 T1 T2 T3 DRAM space read Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.49 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) Rev.6.
Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External read Tc2 T1 T2 T3 DRAM space write Ti Tc1 Tc2 φ Address bus RD HWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.
Section 6 Bus Controller (BSC) DRAM space read Tr Tp Tc1 External address space read Tc2 Ti T1 DRAM space read T3 T2 Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.51 Example of Idle Cycle Operation after DRAM Access (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) DRAM space read Tp Tr Tc1 External address space write DRAM space read Tc2 Ti T1 T2 T3 Tc1 Tc2 φ Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.
Section 6 Bus Controller (BSC) • Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR. Figure 6.53 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
Section 6 Bus Controller (BSC) Table 6.7 shows whether an idle cycle is inserted or not in mixed access to normal space and DRAM. Table 6.
Section 6 Bus Controller (BSC) Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space write Normal space read 0 — — — — Disabled 1 — — — 0 1 state inserted 1 2 states inserted DRAM/ space read DRAM/ space write Normal space read DRAM/ space read 0 — — — — Disabled 1 — — — 0 1 state inserted 1 2 states inserted 0 — — — — Disabled 1 — — — 0 1 state inserted 1 2 states inserted 0 — — — — Disabled 1 — — — 0 1 state inser
Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 DRAM space write Tc2 Ti Tc1 Tc2 φ Address bus RASn (CSn) UCAS, LCAS HWR OE (RD) Data bus Note: n = 2, 3 Idle cycle Figure 6.54 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode Rev.6.00 Mar.
Section 6 Bus Controller (BSC) 6.8.2 Pin States in Idle Cycle Table 6.8 shows the pin states in an idle cycle. Table 6.8 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance CSn (n = 7 to 0) UCAS, LCAS High*1*2 High*2 AS High RD High OE High HWR, LWR High DACKn (n = 1, 0) High Notes: 1. Remains low in DRAM space RAS down mode. 2. Remains low in a DRAM space refresh cycle. 6.
Section 6 Bus Controller (BSC) On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 φ Internal address bus Internal memory Internal I/O register address Internal read signal A23 to A0 External address CSn External space write HWR, LWR D15 to D0 Figure 6.55 Example of Timing when Write Data Buffer Function is Used Rev.6.00 Mar.
Section 6 Bus Controller (BSC) 6.10 Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters continue to operate as long as there is no external access. If any of the following requests are issued in the external bus released state, the BREQO signal can be driven low to output a bus request externally.
Section 6 Bus Controller (BSC) (High) External bus release > External access by internal bus master (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > External bus release (Low) 6.10.2 Pin States in External Bus Released State Table 6.9 shows pin states in the external bus released state. Table 6.
Section 6 Bus Controller (BSC) 6.10.3 Transition Timing Figure 6.56 shows the timing for transition to the bus released state. External space access cycle CPU cycle External bus released state T1 T2 φ High impedance Address bus High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO [1] [2] [3] [4] [5] [6] [1] Low level of BREQ signal is sampled at rise of φ. [2] Bus control signal returns to be high at end of external space access cycle.
Section 6 Bus Controller (BSC) 6.11 Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations (bus arbitration). There are three bus masters—the CPU, DTC, and DMAC—which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
Section 6 Bus Controller (BSC) 6.11.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus.
Section 6 Bus Controller (BSC) 6.12 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 6.13 Usage Notes 6.13.
Section 6 Bus Controller (BSC) 6.13.4 BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ. Rev.6.00 Mar.
Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.
Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1. Internal address bus Address buffer DMAWER DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Channel 1 DMATCR MAR_0AH ETCR_0A MAR_0BH ETCR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH Internal data bus DMA write enable register DMA terminal control register DMA band control register (for all channels) DMA control register Memory address register I/O address register Execute transfer count register Figure 7.
Section 7 DMA Controller (DMAC) 7.2 Input/Output Pins Table 7.1 summarizes the pins of the interrupt controller. Table 7.1 Pin Configuration Channel Pin Name Symbol I/O Function 0 DMA request 0 DREQ0 Input Channel 0 external request DMA transfer acknowledge 0 DACK0 Output Channel 0 single address transfer acknowledge DMA transfer end 0 TEND0 Output Channel 0 transfer end 1 7.
Section 7 DMA Controller (DMAC) • • • • • DMA control register_1B (DMACR_1B) DMA band control register H (DMABCRH) DMA band control register L (DMABCRL) DMA write enable register (DMAWER) DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode). The transfer mode can be selected by means of the FAE1 and FAE0 bits in DMABCRH.
Section 7 DMA Controller (DMAC) 7.3.1 Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified.
Section 7 DMA Controller (DMAC) 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The DMA has four ETCR registers: ETCR_0A in channel 0 (channel 0A), ETCR_0B in channel 0 (channel 0B), ETCR_1A in channel 1 (channel 1A), and ETCR_1B in channel 1 (channel 1B). ETCR is not initialized by a reset or in standby mode.
Section 7 DMA Controller (DMAC) 7.3.4 DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 4 DTDIR 0 R/W Data Transfer Direction Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W 2 DTF2 0 R/W • Channel B 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter conversion end interrupt 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt 0101: Activated by SCI channel 0 recep
Section 7 DMA Controller (DMAC) Full Address Mode: • DMACR_0A and DMACR_1A Bit Bit Name Initial Value R/W Description 15 DTSZ 0 R/W Data Transfer Size Selects the size of data to be transferred at one time.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 10 to 8 ⎯ All 0 R/W Reserved Though these bits can be read from or written to, the write value should always be 0. Legend: ×: Don't care • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved Though this bit can be read from or written to, the write value should always be 0.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 2 1 0 DTF3 DTF2 DTF1 DTF0 0 0 0 0 R/W R/W R/W R/W • Normal Mode 0000: Setting prohibited 0001: Setting prohibited 0010: Activated by DREQ pin falling edge input (for the first transfer after data transfer is enabled, activated by DREQ pin low-level input) 0011: Activated by DREQ pin low-level input 010×: Setting prohibited 0110: Auto-request (cycle steal) 0111: Auto-request (burst) 1×××: Setting prohibited • Block Transfer
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel Operation. Legend: ×: Don't care 7.3.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 12 SAE0 0 R/W Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode.
Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTE1B 0 R/W Data Transfer Enable 1B 6 DTE1A 0 R/W Data Transfer Enable 1A 5 DTE0B 0 R/W Data Transfer Enable 0B 4 DTE0A 0 R/W Data Transfer Enable 0A If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTIE1B 0 R/W Data Transfer End Interrupt Enable 1B 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A 1 DTIE0B 0 R/W Data Transfer End Interrupt Enable 0B 0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
Section 7 DMA Controller (DMAC) Full Address Mode: • DMABCRH Bit Bit Name Initial Value R/W Description 15 FAE1 0 R/W Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1. 0: Short address mode 1: Full address mode 14 FAE0 0 R/W Full Address Enable 0 Specifies whether channel 0 is to be used in short address mode or full address mode.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W 11 DTA1 0 R/W Description Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE1 = 1 and DTA1 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 9 DTA0 0 R/W Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer. When DTE0 = 1 and DTA0 = 1, the internal interrupt source does not issue an interrupt request to the CPU or DTC.
Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTME1 0 R/W Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1. If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 6 DTE1 0 R/W Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 DTME0 0 R/W Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0. If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 4 DTE0 0 R/W Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. When DTE1 is cleared to 0 while this bit is set to 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
Section 7 DMA Controller (DMAC) chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of other channels. First transfer area MAR_0A IOAR_0A ETCR_0A MAR_0B IOAR_0B ETCR_0B MAR_1A DTC IOAR_1A ETCR_1A MAR_1B IOAR_1B ETCR_1B Second transfer area using chain transfer DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B DMABCR Figure 7.
Section 7 DMA Controller (DMAC) 7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. In short address mode, the TEND pin is only available for channel B. The transfer end signal indicates the transfer cycle in which the transfer counter has become 0 regardless of the transfer source.
Section 7 DMA Controller (DMAC) 7.4 Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.
Section 7 DMA Controller (DMAC) 7.4.1 Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant.
Section 7 DMA Controller (DMAC) Note: * If the relevant port is set as an output pin for another function, DMA transfers using the channel in question cannot be guaranteed. 7.4.3 Activation by Auto-Request Auto-request is activated by register setting only, and transfer continues to the end. With autorequest activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred.
Section 7 DMA Controller (DMAC) 7.5 Operation 7.5.1 Transfer Modes Table 7.4 lists the DMAC transfer modes. Table 7.
Section 7 DMA Controller (DMAC) Transfer Mode Transfer Source Remarks Short address mode • TPU channel 0 to 5 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt A/D converter conversion end interrupt External request • Auto-request • Full address mode Single address mode • 1-byte or 1-word transfer for a single transfer request • 1-bus cycle transfer by means of DACK pin instead of using address for specifying I/O • Sequential mode, idle mo
Section 7 DMA Controller (DMAC) 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.5 summarizes register functions in sequential mode. Table 7.
Section 7 DMA Controller (DMAC) Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends.
Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Sequential mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR.
Section 7 DMA Controller (DMAC) 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.
Section 7 DMA Controller (DMAC) ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can only be specified for channel B. Figure 7.
Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Idle mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR.
Section 7 DMA Controller (DMAC) 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues.
Section 7 DMA Controller (DMAC) restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR – (–1)DTID · 2DTSZ · ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit in DMABCRL is cleared. To end the transfer operation, therefore, the DTE bit should be cleared to 0. A transfer end interrupt request is not sent to the CPU or DTC.
Section 7 DMA Controller (DMAC) Transfer Address T IOAR 1 byte or word transfer performed in response to 1 transfer request Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Address B Figure 7.
Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Repeat mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL.
Section 7 DMA Controller (DMAC) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.
Section 7 DMA Controller (DMAC) Address T DACK Transfer 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Rev.6.00 Mar.
Section 7 DMA Controller (DMAC) Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR.
Section 7 DMA Controller (DMAC) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.
Section 7 DMA Controller (DMAC) Transfer Address TA Address TB Address BB Address BA Legend: Address TA = LA Address TB = LB Address BA = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) Address BB = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) Where : LA = Value set in MARA LB = Value set in MARB N = Value set in ETCRA Figure 7.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests.
Section 7 DMA Controller (DMAC) [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Normal mode setting Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA.
Section 7 DMA Controller (DMAC) 7.5.7 Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB.
Section 7 DMA Controller (DMAC) Address TB Address TA 1st block 2nd block Block area Transfer Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M·N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.
Section 7 DMA Controller (DMAC) Address TA Address TB Block area Transfer 1st block Consecutive transfer of M bytes or words is performed in response to one request Address BA 2nd block Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7.
Section 7 DMA Controller (DMAC) ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit in DMABCRL is cleared and transfer ends. If the DTIE bit in DMABCRL is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7.15 shows the operation flow in block transfer mode.
Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Section 7 DMA Controller (DMAC) 7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
Section 7 DMA Controller (DMAC) DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.18 Example of Short Address Mode Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Section 7 DMA Controller (DMAC) DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one bus cycle is executed by the CPU or DTC.
Section 7 DMA Controller (DMAC) DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Last transfer cycle Bus release Bus release Burst transfer Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.
Section 7 DMA Controller (DMAC) DMA read DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Block transfer Bus release Last block transfer Bus release Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) A one-block transfer is performed for a single transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Section 7 DMA Controller (DMAC) DMA read Bus release DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination φ DREQ Address bus DMA control Channel Transfer source Transfer destination Idle Read Write Idle Read Request clear period Request [1] [2] Idle Request clear period Request Minimum of 2 cycles Write Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level i
Section 7 DMA Controller (DMAC) 1 block transfer DMA read Bus release 1 block transfer DMA write DMA Bus dead release DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Idle Read Request Transfer destination Write Dead Request clear period Idle [2] Read Write Transfer destination Dead Idle Request clear period Request Minimum of 2 cycles [1] Transfer source Minimum of 2 cycles [3] [4] [5] [6] [7] Acceptance resumes Acceptance re
Section 7 DMA Controller (DMAC) Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
Section 7 DMA Controller (DMAC) 1 block transfer DMA read Bus release 1 block transfer DMA write DMA Bus dead release DMA read DMA write DMA dead Bus release φ DREQ Address bus DMA control Channel Transfer source Idle Read Dead Write Request clear period Request Idle [2] Read Write Transfer destination Dead Idle Request clear period Request Minimum of 2 cycles [1] Transfer source Transfer destination Minimum of 2 cycles [3] [4] [5] [6] Acceptance resumes [7] Acceptance res
Section 7 DMA Controller (DMAC) DMA read DMA read DMA DMA read dead DMA read φ Address bus RD DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.26 Example of Single Address Mode Transfer (Byte Read) Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
Section 7 DMA Controller (DMAC) In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
Section 7 DMA Controller (DMAC) DMA write DMA write DMA write DMA dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
Section 7 DMA Controller (DMAC) Bus release DMA single Bus release DMA single Bus release φ DREQ Transfer source/ destination Address bus Transfer source/ destination DACK DMA control Channel Single Idle Request Single Idle Request clear period [1] [2] Request clear period Request Minimum of 2 cycles Idle Minimum of 2 cycles [3] [4] [5] Acceptance resumes [6] [7] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ, an
Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level.
Section 7 DMA Controller (DMAC) When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.
Section 7 DMA Controller (DMAC) Figure 7.33 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 7.
Section 7 DMA Controller (DMAC) If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released, the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.11. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7.
Section 7 DMA Controller (DMAC) When the DMAC accesses internal space (on-chip memory or an internal I/O register), the DMAC cycle may be executed at the same time as a refresh cycle or external bus release cycle. 7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes.
Section 7 DMA Controller (DMAC) 7.5.15 Forced Termination of DMAC Operation If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL. Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
Section 7 DMA Controller (DMAC) 7.5.16 Clearing Full Address Mode Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and DTME bit in DMABCRL to 0, or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0.
Section 7 DMA Controller (DMAC) 7.6 Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.
Section 7 DMA Controller (DMAC) 7.7 Usage Notes 7.7.1 DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
Section 7 DMA Controller (DMAC) • If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA internal address DMA control Idle DMA register operation DMA read Transfe source Transfer destination Read Write [1] DMA write Idle [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.
Section 7 DMA Controller (DMAC) • Write data buffer function and DMAC register setting If the setting of a register that controls external accesses is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. Registers that control external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access.
Section 7 DMA Controller (DMAC) DMA read DMA write φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 7.41 Example in which Low Level is Not Output at TEND Pin 7.7.5 Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
Section 7 DMA Controller (DMAC) When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. 7.7.7 Internal Interrupt after End of Transfer When the DTE bit in DMABCRL is cleared to 0 at the end of a transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU or DTC even if the DTA bit in DMABCRH is set to 1.
Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. 8.1 Features • Transfer possible over any number of channels • Three transfer modes ⎯ Normal mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2. From 1 to 65,536 transfers can be specified.
Section 8 Data Transfer Controller (DTC) Internal address bus On-chip RAM CPU interrupt request Register information MRA MRB CRA CRB DAR SAR Control logic DTC DTC activation request Interrupt request DTVECR DTCERA to DTCERG Interrupt controller Internal data bus Legend: MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERG: DTVECR: DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC destination address register DTC enable registers A to G DTC vector regist
Section 8 Data Transfer Controller (DTC) 8.2 Register Descriptions DTC has the following registers. • • • • • • DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
Section 8 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 3 2 MD1 MD0 Undefined Undefined − − DTC Mode These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 1 DTS Undefined − DTC Transfer Mode Select Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Section 8 Data Transfer Controller (DTC) 8.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE Undefined − DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 8.5.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTCER is not performed.
Section 8 Data Transfer Controller (DTC) 8.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL).
Section 8 Data Transfer Controller (DTC) 8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) DTCER which is comprised of seven registers, DTCERA to DTCERG, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 8.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing.
Section 8 Data Transfer Controller (DTC) 8.2.8 DTC Vector Register (DTVECR) DTVECR enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Bit Name Initial Value R/W Description 7 SWDTE 0 R/W DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit.
Section 8 Data Transfer Controller (DTC) 8.3 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI_0.
Section 8 Data Transfer Controller (DTC) Source flag cleared Clear controller Clear DTCER On-chip supporting module IRQ interrupt Interrupt request Selection circuit Select DTVECR Clear request DTC CPU Interrupt controller Interrupt mask Figure 8.2 Block Diagram of DTC Activation Source Control 8.4 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Section 8 Data Transfer Controller (DTC) Lower addresses 0 Start address of register information 1 2 3 MRA SAR MRB DAR Register information CRB CRA Chain transfer MRA SAR MRB DAR CRB CRA Register information for second transfer in case of chain transfer Four bytes Figure 8.3 Correspondence between DTC Vector Address and Register Information DTC vector address Register information start address Register information Chain transfer Figure 8.
Section 8 Data Transfer Controller (DTC) Table 8.
Section 8 Data Transfer Controller (DTC) Origin of Activation Source Activation Source DTC Vector Number Vector Address DTCE* Priority TMR_0 CMIA0 72 H'0490 DTCEE3 High CMIB0 73 H'0492 DTCEE2 CMIA1 76 H'0498 DTCEE1 CMIB1 77 H'049A DTCEE0 DMTEND0A 80 H'04A0 DTCEF7 DMTEND0B 81 H'04A2 DTCEF6 DMTEND1A 82 H'04A4 DTCEF5 TMR_1 DMAC DMTEND1B 83 H'04A6 DTCEF4 RXI0 89 H'04B2 DTCEF3 TXI0 90 H'04B4 DTCEF2 RXI1 93 H'04BA DTCEF1 TXI1 94 H'04BC DTCEF0 RXI2 97 H'04
Section 8 Data Transfer Controller (DTC) 8.5 Operation The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information that is already stored in the on-chip RAM and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer data over any required number of channels.
Section 8 Data Transfer Controller (DTC) Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? Yes No CHNS = 0? Yes Transfer counter = 0 or DISEL = 1? No No Yes Transfer counter = 0? Yes No DISEL = 1? Yes No Clear activation flag Clear DTCER End Interrupt exception handling Figure 8.5 Flowchart of DTC Operation Rev.6.00 Mar.
Section 8 Data Transfer Controller (DTC) Table 8.
Section 8 Data Transfer Controller (DTC) SAR DAR Transfer Figure 8.6 Memory Mapping in Normal Mode 8.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 8.5 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Section 8 Data Transfer Controller (DTC) SAR or DAR DAR or SAR Repeat area Transfer Figure 8.7 Memory Mapping in Repeat Mode 8.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 8.6 lists the register function in block transfer mode. The block size is 1 to 256.
Section 8 Data Transfer Controller (DTC) First block SAR or DAR Block area Transfer DAR or SAR Nth block Figure 8.8 Memory Mapping in Block Transfer Mode 8.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the operation of chain transfer.
Section 8 Data Transfer Controller (DTC) Source Destination Register information CHNE=1 DTC vector address Register information start address Register information CHNE=0 Source Destination Figure 8.9 Operation of Chain Transfer 8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated.
Section 8 Data Transfer Controller (DTC) 8.5.6 Operation Timing φ DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 8.
Section 8 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer information write Transfer information read Transfer information write Figure 8.12 DTC Operation Timing (Example of Chain Transfer) 8.5.7 Number of DTC Execution States Table 8.7 lists execution status for a single DTC data transfer, and table 8.7 shows the number of states required for each execution status.
Section 8 Data Transfer Controller (DTC) Table 8.
Section 8 Data Transfer Controller (DTC) 8.6 Procedures for Using DTC 8.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1. Set the enable bits for the interrupt sources to be used as the activation sources to 1.
Section 8 Data Transfer Controller (DTC) 8.7 Examples of Use of the DTC 8.7.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
Section 8 Data Transfer Controller (DTC) 2. Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer register information consecutively after the NDR transfer register information. 4.
Section 8 Data Transfer Controller (DTC) 4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5.
Section 8 Data Transfer Controller (DTC) 8.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
Section 8 Data Transfer Controller (DTC) 8.8 Usage Notes 8.8.1 Module Stop Mode Setting DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting module stop mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 23, Power-Down Modes. 8.8.2 On-Chip RAM The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM.
Section 8 Data Transfer Controller (DTC) Rev.6.00 Mar.
Section 9 I/O Ports Section 9 I/O Ports Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR or DDR register.
Section 9 I/O Ports Table 9.
Section 9 I/O Ports Mode 7 Port Description Mode 1* Mode 2* Port 5 General I/O port also functioning as interrupt inputs, A/D converter inputs, and SCI I/Os P53/ADTRG/IRQ3 Port 8 General I/O port also functioning as SCI I/Os P85/SCK3 Mode 4 EXPE = 1 EXPE = 0 Input/ Output Type Schmitttriggered input when used as IRQ input P52/SCK2/IRQ2 P51/RxD2/IRQ1 P50/TxD2/IRQ0 P83/RxD3 P81/TxD3 P95/AN13/DA3 Port 9 Dedicated input port also P94/AN12/DA2 functioning as A/D converter analog inputs and D/A conv
Section 9 I/O Ports Mode 7 Port Description Port C General I/O port also functioning as address outputs Port D General I/O port also functioning as data I/Os Port E General I/O port also functioning as data I/Os Port F General I/O port also functioning as interrupt inputs and bus control I/Os Mode 1* Mode 2* Mode 4 EXPE = 1 EXPE = 0 A7 PC7/A7 PC7/A7 PC7 A6 PC6/A6 PC6/A6 PC6 A5 PC5/A5 PC5/A5 PC5 A4 PC4/A4 PC4/A4 PC4 A3 PC3/A3 PC3/A3 PC3 A2 PC2/A2 PC2/A2 PC2 A1 PC1/A1 PC1/
Section 9 I/O Ports Mode 7 Port Port G General I/O port also functioning as bus control I/Os Note: 9.1 * EXPE = 1 EXPE = 0 PG6/BREQ PG6/BREQ PG6 PG5/BACK PG5/BACK PG5 PG4/CS4/BREQO PG4/CS4/ BREQO PG4 PG3/CS3/RAS3 PG3/CS3/ RAS3 PG3 PG2/CS2/RAS2 PG2/CS2/ RAS2 PG2 PG1/CS1 PG1/CS1 PG1 PG0/CS0 PG0/CS0 PG0 Mode 1* Description Mode 2* Mode 4 Input/ Output Type Only modes 1 and 2 are available in the ROMless version.
Section 9 I/O Ports 9.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 9.1.3 Port 1 Register (PORT1) PORT1 shows the pin states. PORT1 cannot be modified.
Section 9 I/O Ports 9.1.4 Pin Functions Port 1 pins also function as the pins for PPG outputs, TPU I/Os, and DMAC outputs. The correspondence between the register specification and the pin functions is shown below.
Section 9 I/O Ports • P16/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH, and bit P16DDR. TPU channel 2 settings (1) in table below (2) in table below P16DDR — 0 1 1 NDER14 — — 0 1 TIOCA2 output P16 input Pin function P16 output TIOCA2 input* Note: PO14 output 1 1.
Section 9 I/O Ports • P15/PO13/TIOCB1/TCLKC/DACK1 The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13 in NDERH, bit SAE1 in DMA BCRH and bit P15DDR.
Section 9 I/O Ports • P14/PO12/TIOCA1/DACK0 The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH, bit SAE0 in DMABCRH and bit P14DDR.
Section 9 I/O Ports • P13/PO11/TIOCD0/TCLKB/TEND1 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11 in NDERH, bit TEE1 in DMATCR of DMAC and bit P13DDR.
Section 9 I/O Ports • P12/PO10/TIOCC0/TCLKA/TEND0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH, bit TEE0 in DMATCR of DMAC and bit P12DDR.
Section 9 I/O Ports • P11/PO9/TIOCB0/DREQ1 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH, and bit P11DDR.
Section 9 I/O Ports • P10/PO8/TIOCA0/DREQ0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH, and bit P10DDR. TPU channel 0 settings (1) in table below (2) in table below P10DDR — 0 1 1 NDER8 — — 0 1 TIOCA0 output P10 input Pin function P10 output PO8 output TIOCA0 input* 1 DREQ0 input Note: 1.
Section 9 I/O Ports 9.2 Port 2 Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 register (PORT2) 9.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W 9.2.3 Port 2 Register (PORT2) PORT2 shows the pin states. PORT2 cannot be modified.
Section 9 I/O Ports 9.2.4 Pin Functions Port 2 pins also function as PPG outputs, TPU I/Os, and TMR I/Os. The correspondence between the register specification and the pin functions is shown below. • P27/PO7/TIOCB5 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL, and bit P27DDR.
Section 9 I/O Ports • P26/PO6/TIOCA5 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL, and bit P26DDR. TPU channel 5 settings (1) in table below (2) in table below P26DDR — 0 1 1 NDER6 — — 0 1 TIOCA5 output P26 input Pin function P26 output PO6 output TIOCA5 input* Note: 1 1.
Section 9 I/O Ports • P25/PO5/TIOCB4/TMO1 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER5 in NDERL, bit P25DDR, and bits OS3 to USO in TCSRI of TMR.
Section 9 I/O Ports • P24/PO4/TIOCA4/RxD4/TMO0 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR4), bit NDER4 in NDERL, bit RE in SCI_4, bit P24DDR, and bit OS3 to OS0 in TCSRO of TMR.
Section 9 I/O Ports • P23/PO3/TIOCD3/TXD4/TMCI1 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL, bit TE in SCR of SCI_4, and bit P23DDR.
Section 9 I/O Ports • P22/PO2/TIOCC3/TMCI0 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL, and bit P22DDR. TPU channel 3 settings (1) in table below (2) in table below P22DDR — 0 1 1 NDER2 — — 0 1 TIOCC3 output P22 input P22 output Pin function PO2 output TIOCC3 input* 2 TMCI0 input* 1 Notes: 1.
Section 9 I/O Ports • P21/PO1/TIOCB3/TMRI1 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL, and bit P21DDR. TPU channel 3 settings (1) in table below (2) in table below P21DDR — 0 1 1 NDER1 — — 0 1 TIOCB3 output P21 input P21 output Pin function PO1 output TIOCB3 input* 2 TMRI1 input* 1 Notes: 1.
Section 9 I/O Ports • P20/PO0/TIOCA3/TMRI0 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL, and bit P20DDR. TPU channel 3 settings (1) in table below (2) in table below P20DDR — 0 1 1 NDER0 — — 0 1 TIOCA3 output P20 input P20 output Pin function PO0 output TIOCA0 input* 2 TMRI0 input* 1 Notes: 1.
Section 9 I/O Ports 9.3 Port 3 Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers. • • • • • Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open drain control register (P3ODR) Port function control register 2(PFCR2) 9.3.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3. P3DDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W 7, 6 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified. 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 9.3.3 Output data for a pin is stored when the pin function is specified to a general purpose I/O. Port 3 Register (PORT3) PORT3 shows the pin states.
Section 9 I/O Ports 9.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls the output status for each port 3 pin. Bit Bit Name Initial Value R/W 7, 6 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified.
Section 9 I/O Ports 9.3.5 Port Function Control Register 2 (PFCR2) PFCR2 controls the I/O port. Bit Bit Name Initial Value R/W 7 to 4 — All 0 — 3 ASOE Description Reserved These bits are always read as 0 and cannot be modified. 1 R/W AS Output Enable Selects to enable or disable the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as AS output pin 2 LWROE 1 R/W LWR Output Enable Selects to enable or disable the LWR output pin.
Section 9 I/O Ports 9.3.6 Pin Functions Port 3 pins also function as the pins for SCI I/Os, I2C output, and a bus control signal output. The correspondence between the register specification and the pin functions is shown below. • P35/SCK1/SCL0/(OE) The pin function is switched as shown below according to the combination of the ICE bit in ICCRA of I2C_0, C/A bit in SMR of SCI_1, bits CKE0 and CKE1 in SCR, bits OEE in DRAMCR, bit OES in PFCR2, and bit P35DDR.
Section 9 I/O Ports • P34/SCK0/SCK4/SDA0 The pin function is switched as shown below according to the combination of bit ICE in ICCRA of I2C_0, bit C/A in SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. ICE 0 CKE1 0 C/A 0 CKE0 P34DDR Pin function 1 1 0 0 1 P34 input P34 output*1 1 — — — 1 — — — — — — — SCK0/SCK4 SCK0/SCK4 SCK0/SCK4 output*1*3 output*1*3 input SDA0 I/O*2 Notes: 1. NMOS open-drain output when P34ODR = 1. 2. NMOS open-drain output regardless of P34ODR 3.
Section 9 I/O Ports • P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_1 and bit P31DDR. TE 0 P31DDR Pin function Note: * 1 0 1 — P31 input P31 output* TxD1 output* NMOS open-drain output when P31ODR = 1. • P30/TxD0/IrTxD The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_0 and bit P30DDR.
Section 9 I/O Ports 9.4 Port 4 Port 4 is an 8-bit input-only port. Port 4 has the following register. • Port 4 register (PORT4) 9.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows port 4 pin states. PORT4 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P47 R The pin states are always read from this register.
Section 9 I/O Ports 9.4.2 Pin Functions Port 4 also functions as the pins for A/D converter analog input and D/A converter analog output. The correspondence between pins are as follows. P47/AN7/(IRQ7) Pin function AN7 input IRQ7 interrupt input* Note: * IRQ7 input when bit ITS7 in ITSR is 1. P46/AN6/DA0/(IRQ6) Pin function AN6 input IRQ6 interrupt input* Note: * IRQ6 input when bit ITS6 in ITSR is 1.
Section 9 I/O Ports P42/AN2/(IRQ2) Pin function AN2 input IRQ2 interrupt input* Note: * IRQ2 input when bit ITS2 in ITSR is 1. P41/AN1/(IRQ1) Pin function AN1 input IRQ1 interrupt input* Note: * IRQ1 input when bit ITS1 in ITSR is 1. P40/AN0/(IRQ0) Pin function AN0 input IRQ0 interrupt input* Note: * IRQ0 input when bit ITS0 in ITSR is 1. Rev.6.00 Mar.
Section 9 I/O Ports 9.5 Port 5 Port 5 is a 4-bit I/O port. The port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) • Port 5 register (PORT5) 9.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.5.3 Port 5 Register (PORT5) PORT5 shows the pin states. PORT5 cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4 — Undefined R Reserved 3 P53 —* R 2 P52 R 1 P51 —* —* 0 P50 —* R Note: Undefined values are read from these bits. * 9.5.4 R If bits P53 to P50 are read while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read.
Section 9 I/O Ports • P52/SCK2/IRQ2 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR. CKE1 0 C/A 0 CKE0 0 P52DDR Pin function Note: 1 * 1 — 1 — — — 0 1 — P52 input P52 output SCK2 output — SCK2 output IRQ2 interrupt input* SCK2 input IRQ2 input when ITS2 = 0.
Section 9 I/O Ports 9.6 Port 8 Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) • Port 8 register (PORT8) 9.6.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8. P8DDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.6.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value R/W 7, 6 — All 0 — Description Reserved These bits are always read as 0 and cannot be modified. 5 P85DR 0 R/W 4 — 0 — 3 P83DR 0 R/W 2 — 0 — 1 P81DR 0 R/W 0 — 0 — 9.6.3 Bits 5, 3, and 1 store output data when the pin function is specified to a general purpose I/O. Bits 4, 2, and 0 are reserved. Port 8 Register (PORT8) PORT8 shows the pin states.
Section 9 I/O Ports 9.6.4 Pin Functions Port 8 pins also function as interrupt inputs and SCI_3 I/Os. The correspondence between the register specification and the pin functions is shown below. • P85/SCK3 The pin function is switched as shown below according to the combination of bit C/A in SMR in SCI_3, bits CKE0 and CKE1 in SCR, and bit P85DDR.
Section 9 I/O Ports 9.7 Port 9 Port 9 is a 2-bit input-only port. Port 9 has the following register. • Port 9 register (PORT9) 9.7.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows port 4 pin states. PORT9 cannot be modified. Bit Bit Name Initial Value R/W Description 7, 6 — Undefined R Reserved P95 —* R 4 P94 —* R The pin states are always read when a port 9 read is performed.
Section 9 I/O Ports 9.8 Port A Port A is an 8-bit I/O port that also has other functions. The port A has the following registers. • • • • • • • Port A data direction register (PADDR) Port A data register (PADR) Port A register (PORTA) Port A MOS zcontrol register (PAPCR) Port A open-drain control register (PAODR) Port function control register 0 (PFCR0) Port function control register 1 (PFCR1) Rev.6.00 Mar.
Section 9 I/O Ports 9.8.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PA7DDR 0 W • 6 PA6DDR 0 W Pins PA4 to PA0 are address outputs.
Section 9 I/O Ports 9.8.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7DR 0 R/W 6 PA6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W 9.8.3 Port A Register (PORTA) PORTA shows port A pin states. PORTA cannot be modified.
Section 9 I/O Ports 9.8.4 Port A MOS Pull-Up Control Register (PAPCR) PAPCR controls the MOS input pull-up function. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PA7PCR 0 R/W 6 PA6PCR 0 R/W When PADDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pullup for that pin.
Section 9 I/O Ports 9.8.6 Port Function Control Register 0 (PFCR0) PFCR0 controls the I/O port. Bit Bit Name Initial Value R/W Description 7 CS7E 1 R/W CS7 to CS0 enable 6 CS6E 1 R/W Enable/disable corresponding CSn output. 5 CS5E 1 R/W 0: Set as I/O port. 4 CS4E 1 R/W 1: Set as CSn output pin. 3 CS3E 1 R/W 2 CS2E 1 R/W 1 CS1E 1 R/W 0 CS0E 1 R/W Rev.6.00 Mar.
Section 9 I/O Ports 9.8.7 Port Function Control Register 1 (PFCR1) PFCR1 performs I/O port control. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 A23E 1 R/W Address 23 Enable Enables or disables output for address output 23 (A23). 0: DR output when PA7DDR = 1 1: A23 output when PA7DDR = 1 6 A22E 1 R/W Address 22 Enable Enables or disables output for address output 22 (A22).
Section 9 I/O Ports Bit Bit Name Initial Value R/W Description 1 A17E 1 R/W Address 17 Enable Enables or disables output for address output 17 (A17). 0: DR output when PA1DDR = 1 1: A17 output when PA1DDR = 1 0 A16E 1 R/W Address 16 Enable Enables or disables output for address output 16 (A16). 0: DR output when PA0DDR = 1 1: A16 output when PA0DDR = 1 9.8.8 Pin Functions Port A pins also function as the pins for address outputs and interrupt inputs.
Section 9 I/O Ports • PA6/A22/IRQ6, PA5/A21/IRQ5 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A22E and A21E, bits IS6 and ITS5 in ITSR, and bit PAnDDR.
Section 9 I/O Ports • PA3/A19, PA2/A18, PA1/A17, PA0/A16 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A19E to A16E, and bit PADDR. Operating mode 1, 2 4 EXPE — — AxxE — PAnDDR — 9.8.
Section 9 I/O Ports 9.9 Port B Port B is an 8-bit I/O port that also has other functions. The port B has the following registers. • • • • Port B data direction register (PBDDR) Port B data register (PBDR) Port B register (PORTB) Port B MOS pull-up control register (PBPCR) 9.9.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.9.2 Port B Data Register (PBDR) PBDR is stores output data for the port B pins. Bit Bit Name Initial Value R/W Description 7 PB7DR 0 R/W 6 PB6DR 0 R/W An output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W 9.9.3 Port B Register (PORTB) PORTB shows port B pin states. PORTB cannot be modified.
Section 9 I/O Ports 9.9.4 Port B MOS Pull-Up Control Register (PBPCR) PBPCR controls the on/off state of MOS input pull-up of port B. PBPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PB7PCR 0 R/W 6 PB6PCR 0 R/W When PBDDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pullup for that pin. 5 PB5PCR 0 R/W 4 PB4PCR 0 R/W 3 PB3PCR 0 R/W 2 PB2PCR 0 R/W 1 PB1PCR 0 R/W 0 PB0PCR 0 R/W 9.9.
Section 9 I/O Ports 9.9.6 Port B MOS Input Pull-Up States Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. Table 9.3 summarizes the MOS input pull-up states. Table 9.
Section 9 I/O Ports 9.10 Port C Port C is an 8-bit I/O port that also has other functions. The port C has the following registers. • • • • Port C data direction register (PCDDR) Port C data register (PCDR) Port C register (PORTC) Port C MOS pull-up control register (PCPCR) 9.10.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.10.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description 7 PC7DR 0 R/W 6 PC6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W 9.10.3 Port C Register (PORTC) PORTC is shows port C pin states. PORTC cannot be modified.
Section 9 I/O Ports 9.10.4 Port C MOS Pull-Up Control Register (PCPCR) PCPCR controls the on/off state of MOS input pull-up of port C. PCPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PC7PCR 0 R/W 6 PC6PCR 0 R/W When PCDDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pullup for that pin. 5 PC5PCR 0 R/W 4 PC4PCR 0 R/W 3 PC3PCR 0 R/W 2 PC2PCR 0 R/W 1 PC1PCR 0 R/W 0 PC0PCR 0 R/W 9.10.
Section 9 I/O Ports 9.10.6 Port C MOS Input Pull-Up States Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis. In modes 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. Table 9.4 summarizes the MOS input pull-up states. Table 9.
Section 9 I/O Ports 9.11 Port D Port D is an 8-bit I/O port that also has other functions. The port D has the following registers. • • • • Port D data direction register (PDDDR) Port D data register (PDDR) Port D register (PORTD) Port D MOS pull-up control register (PDPCR) 9.11.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.11.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W 9.11.3 Port D Register (PORTD) PORTD shows port D pin states. PORTD cannot be modified.
Section 9 I/O Ports 9.11.4 Port D Pull-up Control Register (PDPCR) PDPCR controls on/off states of the input pull-up MOS of port D. PDPCR is valid in mode 7. Bit Bit Name Initial Value R/W Description 7 PD7PCR 0 R/W 6 PD6PCR 0 R/W When PDDDR = 0 (input port), the input pull-up MOS of the input pin is on when the corresponding bit is set to 1. 5 PD5PCR 0 R/W 4 PD4PCR 0 R/W 3 PD3PCR 0 R/W 2 PD2PCR 0 R/W 1 PD1PCR 0 R/W 0 PD0PCR 0 R/W 9.11.
Section 9 I/O Ports 9.11.6 Port D MOS Input Pull-Up States Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis. In mode 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. Table 9.5 summarizes the MOS input pull-up states. Table 9.
Section 9 I/O Ports 9.12 Port E Port E is an 8-bit I/O port that also has other functions. The port E has the following registers. • • • • Port E data direction register (PEDDR) Port E data register (PEDR) Port E register (PORTE) Port E MOS pull-up control register (PEPCR) 9.12.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.12.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7DR 0 R/W 6 PE6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W 9.12.3 Port E Register (PORTE) PORTE shows port E pin states. PORTE cannot be modified.
Section 9 I/O Ports 9.12.4 Port E Pull-up Control Register (PEPCR) PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus mode. Bit Bit Name Initial Value R/W Description 7 PE7PCR 0 R/W 6 PE6PCR 0 R/W When PEDDR = 0 (input port), the input pull-up MOS of the input pin is on when the corresponding bit is set to 1. 5 PE5PCR 0 R/W 4 PE4PCR 0 R/W 3 PE3PCR 0 R/W 2 PE2PCR 0 R/W 1 PE1PCR 0 R/W 0 PE0PCR 0 R/W 9.12.
Section 9 I/O Ports 9.12.6 Port E MOS Input Pull-Up States Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in 8-bit bus mode. MOS input pull-up can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. Table 9.6 summarizes the MOS input pull-up states. Table 9.
Section 9 I/O Ports 9.13.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PF7DDR 1/0* W • 6 PF6DDR 0 W 5 PF5DDR 0 W Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0.
Section 9 I/O Ports 9.13.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description 7 PF7DR 0 R/W 6 PF6DR 0 R/W Output data for a pin is stored when the pin function is specified to a general purpose I/O. 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W 9.13.3 Port F Register (PORTF) PORTF shows port F pin states. PORTF cannot be modified.
Section 9 I/O Ports 9.13.4 Pin Functions Port F pins also function as the pins for external interrupt inputs, bus control signal I/Os, and system clock outputs (φ). The correspondence between the register specification and the pin functions is shown below. • PF7/φ The pin function is switched as shown below according to bit PF7DDR.
Section 9 I/O Ports • PF4/HWR The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PF4DDR. Operating mode 1, 2, 4 7 EXPE — PF4DDR — 0 1 — HWR output PF4 input PF4 output HWR output Pin function 0 1 • PF3/LWR The pin function is switched as shown below according to the operating mode, bit EXPE, bit LWROE, and bit PF3DDR.
Section 9 I/O Ports • PF2/CS6/LCAS The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR.
Section 9 I/O Ports • PF0/WAIT/OE The pin function is switched as shown below according to the operating mode, bit EXPE, bit WAITE, bit OEE in DRAMCR, bit OES in PFCR2, and bit PF0DDR.
Section 9 I/O Ports 9.14 Port G Port G is a 7-bit I/O port that also has other functions. The port G has the following registers. • • • • Port G data direction register (PGDDR) Port G data register (PGDR) Port G register (PORTG) Port Function Control Register 0 (PFCR0) 9.14.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports 9.14.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Bit Name Initial Value R/W Description 7 — 0 — Reserved This bit is always read as 0, and cannot be modified. 6 PG6DR 0 R/W 5 PG5DR 0 R/W 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W 9.14.3 An output data for a pin is stored when the pin function is specified to a general purpose I/O.
Section 9 I/O Ports 9.14.4 Pin Functions Port G pins also function as the pins for bus control signal I/Os. The correspondence between the register specification and the pin functions is shown below. • PG6/BREQ The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, and bit PG6DDR.
Section 9 I/O Ports • PG4/CS4/BREQO The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, bit BREQO, bit CS4E and bit PG4DDR.
Section 9 I/O Ports • PG1/CS1, PG0/CS0 The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, and bit CsnE. Operating mode 1, 2, 4 EXPE — CSnE PGnDDR Pin function 7 0 0 1 1 — 0 1 0 1 0 1 0 1 0 1 0 1 PGn input PGn output PGn input CSn output PGn input PGn output PGn input PGn output PGn input CSn output Legend: n = 1 or 0 Rev.6.00 Mar.
Section 9 I/O Ports Rev.6.00 Mar.
Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively. 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC TGRA activation compare match or input capture TGRA compare match or input capture TGRA compare match or input capture TGRA compare match or input capture TGRA
TGRD TGRB TGRC TGRB A/D conversion start request signal TGRD TGRB TGRB TGRB PPG output trigger signal Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter Figure 10.1 Block Diagram of TPU Rev.6.00 Mar.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Input/Output Pins Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers in each channel.
Section 10 16-Bit Timer Pulse Unit (TPU) • • • • • • • • • • • • • • • • • • • • • • • Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register _4 (TIOR_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) T
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 6 5 CCLR2 CCLR1 CCLR0 0 0 0 R/W R/W R/W Counter Clear 2 to 0 4 3 CKEG1 CKEG0 0 0 R/W R/W Clock Edge 1 and 0 These bits select the TCNT counter clearing source.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.5 TPSC2 to TPSC0 (Channel 0) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 1 0 1 Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.2 Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7, 6 – All 1 – Reserved These bits are always read as 1 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.11 MD3 to MD0 Bit 3 MD3*1 Bit 2 MD2*2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 × — 1 1 0 1 1 × × Legend: ×: Don’t care Notes: 1. MD3 is a reserved bit. The write value should always be 0. 2. Phase counting mode cannot be set for channels 0 and 3.
Section 10 16-Bit Timer Pulse Unit (TPU) TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Bit Bit Name Initial Value R/W Description 7 6 5 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 R/W R/W R/W R/W I/O Control B3 to B0 3 2 1 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 R/W R/W R/W R/W I/O Control A3 to A0 Specify the function of TGRB. For details, see tables 10.12, 10.14, 10.15, 10.16, 10.18, and 10.19. Specify the function of TGRA. For details, see tables 10.20, 10.22, 10.23, 10.24, 10.26, and 10.27.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3 Bit Name TGFD Initial value R/W Description 0 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value R/W Description 0 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7, 6 – – R/W R/W Reserved R/W R/W R/W R/W R/W R/W Timer Synchronization 5 to 0 5 4 3 2 1 0 SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 0 0 0 0 0 0 The write value should always be 0.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 Operation 10.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Section 10 16-Bit Timer Pulse Unit (TPU) 2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10.4 Periodic Counter Operation Rev.6.00 Mar.
Section 10 16-Bit Timer Pulse Unit (TPU) Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. 1. Example of setting procedure for waveform output by compare match Figure 10.5 shows an example of the setting procedure for waveform output by a compare match.
Section 10 16-Bit Timer Pulse Unit (TPU) 2. Examples of waveform output operation Figure 10.6 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA TIOCB No change No change 0 output Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Section 10 16-Bit Timer Pulse Unit (TPU) 2. Example of input capture operation Figure 10.9 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Section 10 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Setting Procedure: Figure 10.10 shows an example of the synchronous operation setting procedure.
Section 10 16-Bit Timer Pulse Unit (TPU) Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 10.4.5, PWM Modes.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.28 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGRA_0 TGRC_0 TGRB_0 TGRD_0 TGRA_3 TGRC_3 TGRB_3 TGRD_3 3 • When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.12.
Section 10 16-Bit Timer Pulse Unit (TPU) Example of Buffer Operation Setting Procedure: Figure 10.14 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. Buffer operation [1] [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. Set buffer operation [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count [3] Select TGR function Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation: 1. When TGR is an output compare register Figure 10.15 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Section 10 16-Bit Timer Pulse Unit (TPU) 2. When TGR is an input capture register Figure 10.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase counting mode. Table 10.29 shows the register combinations used in cascaded operation.
Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation: Figure 10.18 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
Section 10 16-Bit Timer Pulse Unit (TPU) TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 10.21 Example of PWM Mode Operation (1) Figure 10.22 shows an example of PWM mode 2 operation.
Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.23 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Section 10 16-Bit Timer Pulse Unit (TPU) Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 10.24 Example of Phase Counting Mode Setting Procedure Rev.6.00 Mar.
Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.32 summarizes the TCNT up/down-count conditions.
Section 10 16-Bit Timer Pulse Unit (TPU) 2. Phase counting mode 2 Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.26 Example of Phase Counting Mode 2 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 3. Phase counting mode 3 Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 10.27 Example of Phase Counting Mode 3 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 4. Phase counting mode 4 Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 10.28 Example of Phase Counting Mode 4 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function, and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.5 Interrupts There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.9 Operation Timing 10.9.1 Input/Output Timing TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation. φ Internal clock Rising edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 10.30 Count Timing in Internal Clock Operation φ External clock Rising edge Falling edge Falling edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT input clock is generated. Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.35 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 10.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 10.36 and 10.37 show the timings in buffer operation. φ n TCNT n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 10.36 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 10.37 Buffer Operation Timing (Input Capture) Rev.6.00 Mar.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.9.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 10.38 TGI Interrupt Timing (Compare Match) Rev.6.00 Mar.
Section 10 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 10.39 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. φ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.39 TGI Interrupt Timing (Input Capture) Rev.6.00 Mar.
Section 10 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.42 shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T2 T1 φ TSR address Address Write signal Status flag Interrupt request signal Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.10 Usage Notes 10.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 23, Power-Down Modes. 10.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: φ f= (N + 1) Where f: Counter frequency φ: Operating frequency N: TGR set value 10.10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.46 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 10.46 Contention between TCNT Write and Increment Operations 10.10.
Section 10 16-Bit Timer Pulse Unit (TPU) TGR write cycle T2 T1 φ TGR address Address Write signal Compare match signal Disabled TCNT N N+1 TGR N M TGR write data Figure 10.47 Contention between TGR Write and Compare Match 10.10.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10.48 shows the timing in this case.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10.49 shows the timing in this case. TGR read cycle T1 T2 φ TGR address Address Read signal Input capture signal TGR X Internal data bus M M Figure 10.49 Contention between TGR Read and Input Capture Rev.6.00 Mar.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.50 shows the timing in this case. TGR write cycle T1 T2 φ Address TGR address Write signal Input capture signal TCNT M M TGR Figure 10.50 Contention between TGR Write and Input Capture 10.10.
Section 10 16-Bit Timer Pulse Unit (TPU) Buffer register write cycle T1 T2 φ Buffer register address Address Write signal Input capture signal TCNT N M TGR Buffer register N M Figure 10.51 Contention between Buffer Register Write and Input Capture 10.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.53 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 φ TCNT address Address Write signal TCNT TCNT write data H'FFFF M TCFV flag Figure 10.
Section 11 Programmable Pulse Generator (PPG) Section 11 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 11.1 11.
Section 11 Programmable Pulse Generator (PPG) Compare match signals Control logic PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Legend: PMR: PCR: NDERH: NDERL: NDRH: NDRL: PODRH: PODRL: NDERH NDERL PMR PCR Pulse output pins, group 3 PODRH NDRH PODRL NDRL Pulse output pins, group 2 Pulse output pins, group 1 Pulse output pins, group 0 PPG output mode register PPG output control register Next data enable register H Next data enable register L Next data register H Next dat
Section 11 Programmable Pulse Generator (PPG) 11.2 Input/Output Pins Table 11.1 summarizes the I/O pins of the PPG. Table 11.1 Pin Configuration Pin Name I/O Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output PO10 Output PO9 Output PO8 Output PO7 Output PO6 Output PO5 Output PO4 Output PO3 Output PO2 Output PO1 Output PO0 Output 11.
Section 11 Programmable Pulse Generator (PPG) 11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1.
Section 11 Programmable Pulse Generator (PPG) 11.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.
Section 11 Programmable Pulse Generator (PPG) 11.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. • NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Section 11 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 3 NDR11 0 R/W Next Data Register 11 to 8 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. These bits are always read as 1 and cannot be modified.
Section 11 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 3 NDR3 0 R/W Next Data Register 3 to 0 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 11.3.4 These bits are always read as 1 and cannot be modified. PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis.
Section 11 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 1 G0CMS1 1 R/W Group 0 Compare Match Select 1 and 0 0 G0CMS0 1 R/W Select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 11.3.5 PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group.
Section 11 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) 2 G2NOV 0 R/W Group 2 Non-Overlap Selects normal or non-overlapping operation for pulse output group 2.
Section 11 Programmable Pulse Generator (PPG) 11.4 Operation Figure 11.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Section 11 Programmable Pulse Generator (PPG) 11.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ N TCNT TGRA N+1 N Compare match A signal n NDRH PODRH PO8 to PO15 m n m n Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) Rev.6.00 Mar.
Section 11 Programmable Pulse Generator (PPG) 11.4.2 Sample Setup Procedure for Normal Pulse Output Figure 11.4 shows a sample procedure for setting up normal pulse output.
Section 11 Programmable Pulse Generator (PPG) 11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 11.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value Compare match TCNT TGRA H'0000 Time 80 NDRH PODRH 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 PO15 PO14 PO13 PO12 PO11 Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output) 1.
Section 11 Programmable Pulse Generator (PPG) If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. 11.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • NDR bits are always transferred to PODR bits at compare match A. • At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11.
Section 11 Programmable Pulse Generator (PPG) Compare match A Compare match B Write to NDR Write to NDR NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Do not write to NDR here Write to NDR here Figure 11.7 Non-Overlapping Operation and NDR Write Timing Rev.6.00 Mar.
Section 11 Programmable Pulse Generator (PPG) 11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figure 11.8 shows a sample procedure for setting up non-overlapping pulse output.
Section 11 Programmable Pulse Generator (PPG) 11.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 11.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.
Section 11 Programmable Pulse Generator (PPG) 2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0.
Section 11 Programmable Pulse Generator (PPG) 11.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11.9. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRL Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.
Section 11 Programmable Pulse Generator (PPG) 11.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11.11 shows the timing of this output. φ TIOC pin Input capture signal NDR N PODR M PO M N N Figure 11.11 Pulse Output Triggered by Input Capture (Example) 11.
Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Mar.
Section 12 8-Bit Timers (TMR) Section 12 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 12.
Section 12 8-Bit Timers (TMR) Figure 12.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
Section 12 8-Bit Timers (TMR) 12.2 Input/Output Pins Table 12.1 summarizes the pins of the 8-bit timer module. Table 12.
Section 12 8-Bit Timers (TMR) 12.3.2 Time Constant Register A (TCORA) TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled during the T2 state of a TCORA write cycle.
Section 12 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled 6 CMIEA 0 R/W Compare Match Interrupt Enable A Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1.
Section 12 8-Bit Timers (TMR) Table 12.
Section 12 8-Bit Timers (TMR) Bit 6 Bit Name CMFA Initial Value R/W Description 0 R/(W)* Compare Match Flag A [Setting condition] Set when TCNT matches TCORA [Clearing conditions] 5 OVF 0 R/(W)* • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA • When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 Timer Overflow Flag [Setting condition] Set when TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OV
Section 12 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output) Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
Section 12 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 4 — 1 R Reserved This bit is always read as 1 and cannot be modified. 3 2 OS3 OS2 0 0 R/W R/W Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
Section 12 8-Bit Timers (TMR) TCNT H'FF Counter clear TCORA TCORB H'00 TMO Figure 12.2 Example of Pulse Output 12.5 Operation Timing 12.5.1 TCNT Incrementation Timing Figure 12.3 shows the count timing for internal clock input. Figure 12.4 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges.
Section 12 8-Bit Timers (TMR) φ External clock input pin Clock input to TCNT TCNT N–1 N N+1 Figure 12.4 Count Timing for External Clock Input 12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Section 12 8-Bit Timers (TMR) 12.5.3 Timing of Timer Output when Compare-Match Occurs When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Figure 12.6 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 12.6 Timing of Timer Output 12.5.4 Timing of Compare Match Clear TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.
Section 12 8-Bit Timers (TMR) 12.5.5 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12.8 shows the timing of this operation. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 12.8 Timing of Clearance by External Reset 12.5.
Section 12 8-Bit Timers (TMR) 12.6 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 12.6.
Section 12 8-Bit Timers (TMR) 12.7 Interrupts 12.7.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 12.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 12.
Section 12 8-Bit Timers (TMR) 12.8 Usage Notes 12.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows this operation. TCNT write cycle by CPU T1 T2 φ TCNT address Address Internal write signal Counter clear signal N TCNT H'00 Figure 12.10 Contention between TCNT Write and Clear Rev.6.00 Mar.
Section 12 8-Bit Timers (TMR) 12.8.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.11 shows this operation. TCNT write cycle by CPU T1 T2 φ TCNT address Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.11 Contention between TCNT Write and Increment Rev.6.00 Mar.
Section 12 8-Bit Timers (TMR) 12.8.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 12.12. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Inhibited Figure 12.12 Contention between TCOR Write and Compare Match Rev.6.00 Mar.
Section 12 8-Bit Timers (TMR) 12.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 12.4. Table 12.4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 12.8.
Section 12 8-Bit Timers (TMR) Table 12.5 Switching of Internal Clock and TCNT Operation No.
Section 12 8-Bit Timers (TMR) No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N N CKS bit write Notes: 1. 2. 3. 4. 12.8.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
Section 12 8-Bit Timers (TMR) Rev.6.00 Mar.
Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows.
Section 13 Watchdog Timer Clock WDTOVF Internal reset signal* Clock select Reset control RSTCSR TCNT φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources TSCR Module bus Bus interface Internal bus Overflow Interrupt control WOVI (interrupt request signal) WDT Legend: Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by the register setting. Figure 13.1 Block Diagram of WDT 13.
Section 13 Watchdog Timer 13.3 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 13.6.1, Notes on Register Access. • Timer counter (TCNT) • Timer control/status register (TCSR) • Reset control/status register (RSTCSR) 13.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter.
Section 13 Watchdog Timer Bit Bit Name Initial Value R/W Description 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00.
Section 13 Watchdog Timer 13.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Bit 7 Bit Name WOVF Initial Value R/W Description 0 R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode.
Section 13 Watchdog Timer 13.4 Operation 13.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
Section 13 Watchdog Timer TCNT count Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT WDTOVF signal 132 states*2 Internal reset signal*1 518 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Figure 13.2 Operation in Watchdog Timer Mode 13.4.
Section 13 Watchdog Timer TCNT count Overflow H'FF Overflow Overflow Overflow Time H'00 WOVI WT/IT=0 TME=1 WOVI WOVI WOVI Legend: WOVI: Interval timer interrupt request generation Figure 13.3 Operation in Interval Timer Mode 13.5 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 13.
Section 13 Watchdog Timer TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition shown in figure 13.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte data to TCNT or TCSR according to the satisfied condition. To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer instruction cannot perform writing to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit.
Section 13 Watchdog Timer 13.6.2 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13.5 shows this operation. TCNT write cycle T1 T2 Next cycle φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.5 Contention between TCNT Write and Increment 13.6.
Section 13 Watchdog Timer 13.6.5 Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 13.6.
Section 13 Watchdog Timer Rev.6.00 Mar.
Section 14 Serial Communication Interface (SCI, IrDA) Section 14 Serial Communication Interface (SCI, IrDA) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Section 14 Serial Communication Interface (SCI, IrDA) • Average transfer rate generator (SCI_2 only): The following transfer rate can be selected. 115.152 or 460.606 kbps at 10.667-MHz operation 115.196, 460.
Bus interface Section 14 Serial Communication Interface (SCI, IrDA) Module data bus RxD RDR TDR RSR TSR SCMR SSR SCR SMR SEMR BRR φ Baud rate generator Transmission/ reception control TxD Parity generation φ/4 φ/16 φ/64 Clock Parity check External clock SCK Legend: RSR: RDR: TSR: TDR: SMR: SCR: SSR: SCMR: BRR: SEMR: Internal data bus TEI TXI RXI ERI Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Seri
Section 14 Serial Communication Interface (SCI, IrDA) 14.2 Input/Output Pins Table 14.1 shows the serial pins for each SCI channel. Table 14.
Section 14 Serial Communication Interface (SCI, IrDA) 14.3 Register Descriptions The SCI has the following registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions partially differ.
Section 14 Serial Communication Interface (SCI, IrDA) • • • • • • • • • • • • • • • • • Transmit shift register_3 (TSR_3) Receive data register_3 (RDR_3) Transmit data register_3 (TDR_3) Serial mode register_3 (SMR_3) Serial control register_3 (SCR_3) Serial status register_3 (SSR_3) Smart card mode register_3 (SCMR_3) Bit rate register_3 (BRR_3) Receive shift register_4 (RSR_4) Transmit shift register_4 (TSR_4) Receive data register_4 (RDR_4) Transmit data register_4 (TDR_4) Serial mode register_4 (SMR_4
Section 14 Serial Communication Interface (SCI, IrDA) already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. 14.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data.
Section 14 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked regardless of the STOP bit setting.
Section 14 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 GM 0 R/W GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of 1 bit), and clock output control mode addition is performed. For details, refer to section 14.7.8, Clock Output Control.
Section 14 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 1 and 0: 0 CKS0 0 R/W These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 14.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 14.3.
Section 14 Serial Communication Interface (SCI, IrDA) 14.3.6 Serial Control Register (SCR) SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer/receive clock source. For details on interrupt requests, refer to section 14.9, SCI Interrupts. Some bit functions of SCR differ in normal serial communication interface mode and Smart Card interface mode.
Section 14 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1.
Section 14 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1×: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.
Section 14 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled.
Section 14 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W 2 TEIE 0 R/W Description Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. 1 CKE1 0 0 CKE0 0 R/W Clock Enable 1 and 0 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 14.7.8, Clock Output Control.
Section 14 Serial Communication Interface (SCI, IrDA) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode.
Section 14 Serial Communication Interface (SCI, IrDA) Bit 5 Bit Name ORER Initial Value R/W Description 0 R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1.
Section 14 Serial Communication Interface (SCI, IrDA) Bit 3 Bit Name PER Initial Value R/W Description 0 R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1.
Section 14 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF in SCMR is 1) Bit 7 Bit Name TDRE Initial Value R/W 1 1 R/(W)* Description Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and data writing to TDR is enabled.
Section 14 Serial Communication Interface (SCI, IrDA) Bit 5 Bit Name ORER Initial Value R/W Description 0 1 R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1.
Section 14 Serial Communication Interface (SCI, IrDA) Bit 3 Bit Name PER Initial Value R/W Description 0 1 R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1.
Section 14 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEND 1 R Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR.
Section 14 Serial Communication Interface (SCI, IrDA) 14.3.8 Smart Card Mode Register (SCMR) SCMR selects Smart Card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 3 SDIR These bits are always read as 1. 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data format is 8 bits.
Section 14 Serial Communication Interface (SCI, IrDA) 14.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 14.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.
Section 14 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 17.2032 18 19.6608 20 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 3 75 0.48 3 79 –0.12 3 86 0.31 3 88 –0.25 150 2 223 0.00 2 233 0.16 2 255 0.00 3 64 0.16 300 2 111 0.00 2 116 0.16 2 127 0.00 2 129 0.16 600 1 223 0.00 1 233 0.16 1 255 0.00 2 64 0.16 1200 1 111 0.00 1 116 0.16 1 127 0.00 1 129 0.16 2400 0 223 0.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 25 6.2500 390625 30 7.5000 468750 33 34* 8.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) n 8 10 16 N n N n N 20 n N 25 n N 30 n N 3 233 34* 1 33 n N n N 110 250 3 124 — — 3 249 500 2 249 — — 3 124 — — 1k 2 124 — — 2 249 — — 3 97 3 116 3 128 3 128 2.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 25 4.1667 4166666.7 30 5.0000 5000000.0 33 34* 5.5000 5500000.0 5.6667 5666666.7 Note: * Supported only by the H8S/2368 0.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency φ (MHz) 10.00 10.7136 13.00 14.2848 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 1 30 0 1 25 0 1 8.99 0 1 0.00 Operating Frequency φ (MHz) 16.00 18.00 20.00 25.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) φ (MHz) Maximum Bit Rate (bit/s) n N 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 14.2848 19200 0 0 16.00 21505 0 0 18.00 24194 0 0 20.00 26882 0 0 25.00 33602 0 0 30.00 40323 0 0 33.00 44355 0 0 34.00* 45699 0 0 Note: * Supported only by the H8S/2368 0.18 μm F-ZTAT Group. Rev.6.00 Mar.
Section 14 Serial Communication Interface (SCI, IrDA) 14.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit Bit Name Initial Value R/W Description 7 IrE 0 R/W IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output.
Section 14 Serial Communication Interface (SCI, IrDA) 14.3.11 Serial Extension Mode Register (SEMR) SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by selecting the average transfer rate. Bit Bit Name Initial Value R/W Description 7 to 4 — Undefined — Reserved 3 ABCS If these bits are read, an undefined value will be returned. They cannot be modified.
Section 14 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 1 0 ACS2 ACS1 ACS0 0 0 0 R/W R/W R/W Asynchronous clock source selection (valid when CKE1 = 1 in asynchronous mode) Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS. 000: External clock input 001: Selects 115.152 kbps which is the average transfer rate dedicated for φ= 10.667 MHz.
Section 14 Serial Communication Interface (SCI, IrDA) 14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.
Section 14 Serial Communication Interface (SCI, IrDA) 14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched at the middle of each bit by sampling the data at the rising edge of the 8th pulse of the basic clock as shown in figure 14.3.
Section 14 Serial Communication Interface (SCI, IrDA) 14.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
Section 14 Serial Communication Interface (SCI, IrDA) 14.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 14.5. Do not write to SMR, SCMR, IrCR, or SEMR while the SCI is operating. This also applies to writing the same data as the current register contents. When the operating mode, transfer format, etc.
Section 14 Serial Communication Interface (SCI, IrDA) 14.4.5 Data Transmission (Asynchronous Mode) Figure 14.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface (SCI, IrDA) Figure 14.7 shows a sample flowchart for transmission in asynchronous mode. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 14.
Section 14 Serial Communication Interface (SCI, IrDA) [1] Initialization Start of transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 14 Serial Communication Interface (SCI, IrDA) 14.4.6 Serial Data Reception (Asynchronous Mode) Figure 14.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.9 shows a sample flowchart for serial data reception. Table 14.
Section 14 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Section 14 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 14.9 Sample Serial Reception Data Flowchart (2) Rev.6.00 Mar.
Section 14 Serial Communication Interface (SCI, IrDA) 14.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
Section 14 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'AA H'01 (MPB= 1) ID transmission cycle = receiving station specification (MPB= 0) Data transmission cycle = data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 14.
Section 14 Serial Communication Interface (SCI, IrDA) [1] [1] SCI initialization: Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND = 1? Yes No Break output? The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled.
Section 14 Serial Communication Interface (SCI, IrDA) 14.5.2 Multiprocessor Serial Data Reception Figure 14.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 14.
Section 14 Serial Communication Interface (SCI, IrDA) 1 Start bit 0 Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data1) MPB D0 D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 RXI interrupt request (multiprocessor interrupt) generated MPIE = 0 RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine If not this station’s ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again retains its state (a) Data does not
Section 14 Serial Communication Interface (SCI, IrDA) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1. Start of reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ∨ ORER = 1? [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 14 Serial Communication Interface (SCI, IrDA) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.6.00 Mar.
Section 14 Serial Communication Interface (SCI, IrDA) 14.6 Operation in Clocked Synchronous Mode Figure 14.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Section 14 Serial Communication Interface (SCI, IrDA) 14.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 14.15. Do not write to SMR, SCMR, IrCR, or SEMR while the SCI is operating. This also applies to writing the same data as the current register contents. When the operating mode, transfer format, etc.
Section 14 Serial Communication Interface (SCI, IrDA) 14.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 14.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface (SCI, IrDA) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev.6.00 Mar.
Section 14 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin.
Section 14 Serial Communication Interface (SCI, IrDA) 14.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2.
Section 14 Serial Communication Interface (SCI, IrDA) [1] Initialization Start of reception [2] Read ORER flag in SSR Yes [3] ORER = 1? No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 14 Serial Communication Interface (SCI, IrDA) 14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized.
Section 14 Serial Communication Interface (SCI, IrDA) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Start of transmission/reception Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 14 Serial Communication Interface (SCI, IrDA) 14.7 Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 14.7.1 Pin Connection Example Figure 14.21 shows an example of connection with the Smart Card.
Section 14 Serial Communication Interface (SCI, IrDA) 14.7.2 Data Format (Except for Block Transfer Mode) Figure 14.22 shows the transfer data format in Smart Card interface mode. • One frame consists of 8-bit data plus a parity bit in asynchronous mode. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
Section 14 Serial Communication Interface (SCI, IrDA) As in the above sample start character, with the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode.
Section 14 Serial Communication Interface (SCI, IrDA) asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. As shown in figure 14.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the following formula. M = | (0.5 – | D – 0.5 | 1 ) – (L – 0.
Section 14 Serial Communication Interface (SCI, IrDA) 14.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. 2. 3. 4. Clear the TE and RE bits in SCR to 0. Clear the error flags ERS, PER, and ORER in SSR to 0. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR. Set the PE bit to 1. Set the SMIF, SDIR, and SINV bits in SCMR.
Section 14 Serial Communication Interface (SCI, IrDA) 4. Transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is generated. Writing transmit data to TDR transfers the next transmit data. Figure 14.28 shows a flowchart for transmission.
Section 14 Serial Communication Interface (SCI, IrDA) The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag generation timing is shown in figure 14.27. I/O data Ds D0 D1 D2 TXI (TEND interrupt) D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu When GM = 0 11.0etu When GM = 1 Legend: Start bit Ds: D0 to D7: Data bits Parity bit Dp: Error signal DE: Note: etu: Elementary Time Unit (time for transfer of 1 bit) Figure 14.
Section 14 Serial Communication Interface (SCI, IrDA) Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 14.28 Example of Transmission Processing Flow Rev.6.00 Mar.
Section 14 Serial Communication Interface (SCI, IrDA) 14.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 14.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
Section 14 Serial Communication Interface (SCI, IrDA) Start Initialization Start reception ORER = 0 and PER = 0 No Yes Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 14.30 Example of Reception Processing Flow 14.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Section 14 Serial Communication Interface (SCI, IrDA) CKE0 SCK Specified pulse width Specified pulse width Figure 14.31 Timing for Fixing Clock Output Level When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. 1. The initial state is port input and high impedance.
Section 14 Serial Communication Interface (SCI, IrDA) Software standby Normal operation [1] [2] [3] [4] [5] Normal operation [6] [7] Figure 14.32 Clock Halt and Restart Procedure Rev.6.00 Mar.
Section 14 Serial Communication Interface (SCI, IrDA) 14.8 IrDA Operation When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system. In the IrDA specification version 1.
Section 14 Serial Communication Interface (SCI, IrDA) In the specification, the high pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can be set for a high pulse width with a minimum value of 1.41 µs. When the serial data is 1, no pulse is output.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.12 Settings of Bits IrCKS2 to IrCKS0 Bit Rate (bps) (Above) /Bit Period × 3/16 (µs) (Below) Operating Frequency φ (MHz) 2400 9600 19200 38400 57600 115200 78.13 19.53 9.77 4.88 3.26 1.63 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.288 101 101 101 101 101 101 14 101 101 101 101 101 101 14.
Section 14 Serial Communication Interface (SCI, IrDA) 14.9 SCI Interrupts 14.9.1 Interrupts in Normal Serial Communication Interface Mode Table 14.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Section 14 Serial Communication Interface (SCI, IrDA) Table 14.
Section 14 Serial Communication Interface (SCI, IrDA) 14.9.2 Interrupts in Smart Card Interface Mode Table 14.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 14.
Section 14 Serial Communication Interface (SCI, IrDA) When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 8, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1.
Section 14 Serial Communication Interface (SCI, IrDA) 14.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 14.10.
Section 14 Serial Communication Interface (SCI, IrDA) 14.10.7 Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and become high-level output after the relevant mode is cleared.
Section 14 Serial Communication Interface (SCI, IrDA) Figure 14.39 shows a sample flowchart for mode transition during reception. All data transmitted? No [1] [1] Data being transmitted is interrupted. After exiting software standby mode, normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, but note that if the DTC has been activated, the remaining data in DTCRAM will be transmitted when TE and TIE are set to 1.
Section 14 Serial Communication Interface (SCI, IrDA) End of transmission Start of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Port Start Stop Port input/output Port SCI TxD output High output SCI TxD output Figure 14.
Section 14 Serial Communication Interface (SCI, IrDA) Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes module stop mode. Yes Read receive data in RDR RE = 0 Transition to software standby mode Exit from software standby mode Change operating mode? No Yes Initialization RE = 1 Figure 14.39 Sample Flowchart for Mode Transition during Reception Rev.6.00 Mar.
Section 14 Serial Communication Interface (SCI, IrDA) Rev.6.00 Mar.
Section 15 I2C Bus Interface2 (IIC2) (Option) Section 15 I2C Bus Interface2 (IIC2) (Option) An I2C bus interface is an option. When using the optional functions, take notice of the following item: For the masked ROM version, ‘W’ is added to the model name of the product that uses optional functions. For example: HD6432365WTE This LSI has a two-channel I2C bus interface, The I2C bus interface conforms to and provides a subset of the NXP Semiconductors I2C bus (inter-IC bus) interface (Rev.
Section 15 I2C Bus Interface2 (IIC2) (Option) Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCRA ICCRB ICMR Internal data bus Noise canceler ICDRT SDA Output control ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICEIR Legend: ICCRA: ICCRB: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: Interrupt generator I2C bus control register A I2C bus control register B I2C mode register I2C s
Section 15 I2C Bus Interface2 (IIC2) (Option) Vcc SCL in Vcc SCL SCL SDA SDA SCL out SDA in SCL in SCL out SCL SDA (Master) SCL SDA SDA out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I2C bus interface. Table 15.
Section 15 I2C Bus Interface2 (IIC2) (Option) 15.3 Register Descriptions The I2C bus interface has the following registers.
Section 15 I2C Bus Interface2 (IIC2) (Option) 15.3.1 I2C Bus Control Register A (ICCRA) ICCRA is an 8-bit readable/writable register that enables or disables the I2C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description 7 ICE 0 I2C Bus Interface Enable R/W 0: This module is halted. 1: This bit is enabled for transfer operations.
Section 15 I2C Bus Interface2 (IIC2) (Option) Table 15.2 Transfer Rate Bit3 Bit2 Bit1 Bit0 Transfer Rate CKS3 CKS2 CKS1 CKS0 Clock 0* 3 0* 3 1 0 φ= 20MHz φ= 25 MHz φ= 33 MHz φ= 1 34 MHz* φ/28 286 kHz 357 kHz 714 kHz* 893 kHz* 1179 2 kHz* 1 φ/40 200 kHz 250 kHz 500 kHz* 625 kHz* 825 kHz* 850 kHz* 0 φ/48 167 kHz 208 kHz 417 kHz* 521 kHz* 688 kHz* 708 kHz* 1 φ/64 125 kHz 156 kHz 313 kHz 391 kHz* 516 kHz* 531 kHz* 0 0 φ/168 47.6 kHz 59.
Section 15 I2C Bus Interface2 (IIC2) (Option) 15.3.2 I2C Bus Control Register B (ICCRB) ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in I2C control. Bit Bit Name Initial Value R/W Description 7 BBSY 0 Bus Busy R/W 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start and stop conditions in master mode.
Section 15 I2C Bus Interface2 (IIC2) (Option) Bit Bit Name Initial Value R/W 0 ⎯ 1 ⎯ Description Reserved This bit is always read as 1. 15.3.3 I2C Bus Mode Register (ICMR) ICMR performs master mode wait control and selects the transfer bit count. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved 6 WAIT 0 R/W Wait Insertion Bit The write value should always be 0. This bit selects whether to insert a wait after data transfer except for the acknowledge bit.
Section 15 I2C Bus Interface2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. The data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
Section 15 I2C Bus Interface2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 5 RIE 0 Receive interrupt enable R/W This bit enables or disables the receive data full interrupt request (RXI) when a received data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt request (RXI) is disabled. 1: Receive data full interrupt request (RXI) is enabled.
Section 15 I2C Bus Interface2 (IIC2) (Option) 15.3.5 I2C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags and status.
Section 15 I2C Bus Interface2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 4 NACKF 0 No acknowledge detection flag R/W [Setting condition] When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] When 0 is written in NACKF after reading NACKF = 1 Note: When NACKF = 1 is detected, NACKF must be cleared to 0. Subsequent transmission in not made until NACKF is cleared to 0.
Section 15 I2C Bus Interface2 (IIC2) (Option) Bit Bit Name Initial Value R/W Description 1 AAS 0 Slave Address Recognition Flag R/W In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] • When the slave address is detected in slave receive mode • When the general call address is detected in slave receive mode.
Section 15 I2C Bus Interface2 (IIC2) (Option) 15.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the I2C bus shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible. The initial value of ICDRT is H'FF. 15.3.
Section 15 I2C Bus Interface2 (IIC2) (Option) 15.4 Operation 15.4.1 I2C Bus Format Figure 15.3 shows the I2C bus formats. Figure 15.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
Section 15 I2C Bus Interface2 (IIC2) (Option) Legend: S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receiving device drives SDA to low. DATA: Transferred data P: 15.4.2 Stop condition. The master device drives SDA from low to high while SCL is high.
Section 15 I2C Bus Interface2 (IIC2) (Option) receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
Section 15 I2C Bus Interface2 (IIC2) (Option) SCL (master output) 9 SDA (master output) SDA (slave output) 1 2 3 4 5 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 A 7 Bit 1 8 9 Bit 0 A/ TDRE TEND Data n ICDRT ICDRS Data n User [5] Write data to ICDRT. Clear TDRE. processing [6] Issue stop condition. Clear TEND. [7] Set slave receive mode Figure 15.6 Master Transmit Mode Operation Timing 2 15.4.
Section 15 I2C Bus Interface2 (IIC2) (Option) 7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RDRF to 0. Then clear the RCVD bit to 0. 8. The operation returns to the slave receive mode.
Section 15 I2C Bus Interface2 (IIC2) (Option) SCL (master output) 9 SDA (master output) A SDA (slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR Data n Data n-1 User processing [5] Read ICDRR and clear RDRF after setting RCVD. [7] Read ICDRR, clear RDRF, and clear RCVD. [6] Issue stop condition [8] Set slave receive mode Figure 15.8 Master Receive Mode Operation Timing 2 15.4.
Section 15 I2C Bus Interface2 (IIC2) (Option) Slave receive mode SCL (master output) Slave transmit mode 9 1 2 3 4 5 6 7 8 SDA (master output) 9 1 A SCL (slave output) SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT ICDRS Data 1 Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1), and clear TDRE. [2] Write data to ICDRT (data 2), and clear TDRE.
Section 15 I2C Bus Interface2 (IIC2) (Option) Slave receive mode Slave transmit mode SCL (master output) 9 SDA (master output) A 1 2 3 4 5 6 7 8 9 A SCL (slave output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 15.10 Slave Transmit Mode Operation Timing 2 15.4.
Section 15 I2C Bus Interface2 (IIC2) (Option) 3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.
Section 15 I2C Bus Interface2 (IIC2) (Option) SCL (master output) 9 SDA (master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (slave output) SDA (slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [7] Set ACKBT [8] Read ICDRR, and clear RDRF. Figure 15.12 Slave Receive Mode Operation Timing 2 Rev.6.00 Mar. 18, 2009 Page 652 of 980 REJ09B0050-0600 [10] Read ICDRR, and clear RDRF.
Section 15 I2C Bus Interface2 (IIC2) (Option) 15.4.6 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Section 15 I2C Bus Interface2 (IIC2) (Option) Start Initialize Read BBSY in ICCRB [1] Test the status of the SCL and SDA lines.* [2] Select master transmit mode.* [3] Start condition issuance.* [4] Select transmit data for the first byte (slave address + R/W), and clear TDRE to 0. [5] Wait for 1 byte to be transmitted. [6] Test the acknowledge bit, transferred from the specified slave device.
Section 15 I2C Bus Interface2 (IIC2) (Option) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmitting device.* [3] Dummy read ICDDR* [4] Wait for 1 byte to be received. [5] Check if (last receive - 1) [6] Read the receive data, and clear RDRF to 0. [7] Set acknowledge of the final byte. Disable continuous receive (RCVD = 1). [8] Read receive data of (final byte - 1), and clear RDRF to 0.
Section 15 I2C Bus Interface2 (IIC2) (Option) [1] Clear the flag AAS. Slave transmit mode Clear AAS in ICSR [1] [2] Set transmit data for ICDRT (except for the last data), and clear TDRE to 0. Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of the transmit data, and clear TDRE to 0. Read TDRE in ICSR No [3] TDRE=1 ? [5] Wait the transmission end of the last byte. [6] Clear the flag TEND. Yes No [7] Set slave receive mode.
Section 15 I2C Bus Interface2 (IIC2) (Option) Slave receive mode Clear AAS in ICSR [1] Set ACKBT=0 in ICIER [2] No TDRE=0 ? Slave transmit mode Yes No RDRF= 1? Yes [3] Dummy read ICDRR [1] Clear the flag AAS. [2] Set the acknowledge for the transmit device. Read RDRF in ICSR [4] No RDRF=1 ? [3] Dummy read ICDRR. [4] Wait the reception end of 1 byte. Yes The last receive - 1? Yes No Read ICDRR [5] Judge the (last receive - 1). [5] [6] Read the received data, and clear RDRF to 0.
Section 15 I2C Bus Interface2 (IIC2) (Option) 15.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost. Table 15.3 shows the contents of each interrupt request. Table 15.
Section 15 I2C Bus Interface2 (IIC2) (Option) SCL monitor timing reference clock VIH SCL Internal SCL Figure 15.18 Timing of the Bit Synchronous Circuit Table 15.4 Time for monitoring SCL CKS3 CKS2 Time for monitoring SCL 0 0 7.5 tcyc* 1 19.5 tcyc 0 17.5 tcyc 1 41.5 tcyc 1 Note: 15.7 * If the operating frequency exceeds 20 MHz, it may not be possible to maintain the prescribed transfer rate under certain load conditions. A setting other than 7.5 tcyc should therefore be used.
Section 15 I2C Bus Interface2 (IIC2) (Option) 3. I2C bus interface 2 (IIC2) master receive mode When operating in master receive mode with RDRF set to 1, SCL is driven low at the falling edge of the eighth clock cycle. However, when ICDRR is read near the falling edge of the eighth clock cycle, SCL is only fixed low for one clock cycle at the eighth clock cycle of the next receive data, after which SCL is no longer fixed and the ninth clock cycle is output, even if ICDRR is not read.
Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to ten analog input channels to be selected. The block diagram of A/D converter is shown in figure 16.1. 16.1 • • • • • • • • • Features 10-bit resolution Ten input channels Conversion time: 7.
Section 16 A/D Converter Module data bus Vref Bus interface Successive approximations register AVCC 10-bit D/A AVSS A D D R A AN0 + AN1 – AN2 Internal data bus A D D R B Comparator A D D R C A D D R D A D D R E A D D R F A D D R G A D D R H A D C S R A D C R Control circuit AN4 AN5 AN6 Multiplexer AN3 Sample-andhold circuit AN7 AN12 ADI interrupt signal AN13 Conversion start trigger from 8-bit timer or TPU ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: A/D control register
Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The sixteen analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and channel set 1 (AN12 and AN13). Table 16.
Section 16 A/D Converter 16.3 Register Descriptions The A/D converter has the following registers. • • • • • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D data register E (ADDRE) A/D data register F (ADDRF) A/D data register G (ADDRG) A/D data register H (ADDRH) A/D control/status register (ADCSR) A/D control register (ADCR) 16.3.
Section 16 A/D Converter Table 16.2 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1) A/D Data Register which Stores Conversion Result AN0 ⎯ ADDRA AN1 ⎯ ADDRB AN2 ⎯ ADDRC AN3 ⎯ ADDRD AN4 AN12 ADDRE AN5 AN13 ADDRF AN6 ⎯ ADDRG AN7 ⎯ ADDRH Rev.6.00 Mar.
Section 16 A/D Converter 16.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W Description 7 ADF 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Section 16 A/D Converter Bit Bit Name Initial Value R/W Description 3 CH3 0 R/W Channel select 3 to 0 2 CH2 0 R/W 1 CH1 0 R/W Selects analog input together with bits SCANE and SCANS in ADCR. 0 CH0 0 R/W Set the input channel when conversion is stopped (ADST = 0).
Section 16 A/D Converter 16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion start by an external trigger input. It also sets the A/D converter operating mode and the A/D conversion time. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 6 TRGS0 0 R/W These bits select enabling or disabling of the start of A/D conversion by a trigger signal.
Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.
Section 16 A/D Converter 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically, and steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state.
Section 16 A/D Converter (1) φ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay time tD: tSPL: Input sampling time tCONV: A/D conversion time Figure 16.2 A/D Conversion Timing Rev.6.00 Mar.
Section 16 A/D Converter Table 16.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion start delay time tD 18 — 33 10 — 16 6 — 9 4 — 5 Input sampling time tSPL — 127 — — 63 — — 31 — — 15 — A/D conversion time tCONV 515 — 266 131 — 134 67 — 68 530 259 — Note: Values in the table are the number of states. Table 16.
Section 16 A/D Converter 16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the timing.
Section 16 A/D Converter 16.6 A/D Conversion Precision Definitions This LSI’s A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4).
Section 16 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 16.4 A/D Conversion Precision Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 16.5 A/D Conversion Precision Definitions Rev.6.00 Mar.
Section 16 A/D Converter 16.7 Usage Notes 16.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 23, Power-Down Modes. 16.7.
Section 16 A/D Converter 16.7.3 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 16.7.
Section 16 A/D Converter 16.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7, AN12, AN13) should be connected between AVcc and AVss as shown in figure 16.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN15 must be connected to AVss.
Section 16 A/D Converter Table 16.6 Analog Pin Specifications Item Min Max Unit Analog input capacitance — 20 pF Permissible signal source impedance — 5 kΩ Rev.6.00 Mar.
Section 16 A/D Converter Rev.6.00 Mar.
Section 17 D/A Converter Section 17 D/A Converter 17.1 Features D/A converter features are listed below. • • • • • • 8-bit resolution Two output channels Maximum conversion time of 10 µs (with 20 pF load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Setting the module stop mode DAC0004A_000020020100 Rev.6.00 Mar.
Section 17 D/A Converter Internal data bus Bus interface Module data bus Vref D/A DADR3 8-bit DA2 DADR2 DA3 DACR23 AVCC AVSS Control circuit Legend: DADR2: D/A data register 2 DADR3: D/A data register 3 DADR4: D/A data register 4 DACR23: D/A control register 23 Figure 17.1 Block Diagram of D/A Converter Rev.6.00 Mar.
Section 17 D/A Converter 17.2 Input/Output Pins Table 17.1 summarizes the input and output pins of the D/A converter. Table 17.1 Pin Configuration Pin Name Symbol I/O Function Analog power pin AVCC Input Analog power Analog ground pin AVSS Input Analog ground Reference voltage pin Vref Input Reference voltage of D/A converter Analog output pin 2 DA2 Output Channel 2 analog output Analog output pin 3 DA3 Output Channel 3 analog output 17.
Section 17 D/A Converter 17.3.2 D/A Control Register 23 (DACR23) DACR23 control the operation of the D/A converter. Bit Bit Name Initial Value R/W Description 7 DAOE3 0 R/W D/A Output Enable 3 Controls D/A conversion and analog output. 0: Analog output (DA3) is disabled 1: Channel 3 D/A conversion is enabled; analog output (DA3) is enabled 6 DAOE2 0 R/W D/A Output Enable 2 Controls D/A conversion and analog output.
Section 17 D/A Converter Table 17.2 Control of D/A Conversion Bit 5 DAE Bit 7 DAOE3 Bit 6 DAOE2 Description 0 0 0 D/A conversion disabled 1 Channel 2 D/A conversion enabled, channel3 D/A conversion disabled 0 Channel 3 D/A conversion enabled, channel2 D/A conversion disabled 1 Channel 2 and 3 D/A conversions enabled 0 D/A conversion disabled 1 Channel 2 and 3 D/A conversions enabled 1 1 0 1 0 1 17.
Section 17 D/A Converter DADR2 write cycle DADR2 write cycle DACR23 write cycle DACR23 write cycle φ Address DADR2 Conversion data 1 Conversion data 2 DAOE0 DA2 Conversion result 2 Conversion result 1 High-impedance state tDCONV tDCONV Legend: tDCONV: D/A conversion time Figure 17.2 Example of D/A Converter Operation 17.5 17.5.
Section 18 RAM Section 18 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR).
Section 18 RAM Rev.6.00 Mar.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) Section 19 Flash Memory (0.35-μm F-ZTAT Version) The features of the flash memory included in the flash memory version are summarized below. The block diagram of the flash memory is shown in figure 19.1. 19.1 Features • Size Product Classification ROM Size ROM Address H8S/2368 Group 384 kbytes H'000000 to H'05FFFF (Modes 3, 4, and 7) HD64F2367 • Programming/erase methods The flash memory is programmed 128 bytes at a time.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) Internal address bus Module bus Internal data bus (16 bits) FLMCR1 FLMCR2 Bus interface/controller EBR1 Operating mode EBR2 SYSCR Flash memory Legend: FLMCR1: FLMCR2: EBR1: EBR2: SYSCR: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 System control register Figure 19.1 Block Diagram of Flash Memory Rev.6.00 Mar.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.2 Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 19.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 19.1. Figure 19.3 shows boot mode. Figure 19.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) Table 19.1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program* Program/program-verify Erase/erase-verify/program/ program-verify Note: * To be provided by the user, in accordance with the recommended algorithm. Rev.6.00 Mar.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 1. Initial state (1) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.3 Block Configuration Figure 19.5 shows the block configuration of 384-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 384kbyte flash memory is divided into 64 kbytes (5 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is performed in these divided units.
Section 19 Flash Memory (0.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 19.2. Table 19.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 19.7, Flash Memory Programming/Erasing. Bit Bit Name Initial Value R/W Description 7 — 0/1 R This bit is reserved. This bit is always read as 0 in modes 1 and 2. This bit is always read as 1 in modes 3 to 7.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. When the SWE bit in FLMCR1 is cleared to 0, FLMCR2 is initialized to H'00. FLMCR2 is a read-only register, and should not be written to. Bit Bit Name Initial Value R/W Description 7 FLER 0 R Indicates that an error has occurred during an operation on flash memory (programming or erasing).
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Set only one bit in EBR1 and EBR2 together (do not set more than one bit at the same time. Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). For details, see table 19.3.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 7, 6 — All 0 R/W Reserved 5 EB13 0 R/W When this bit is set to 1, 64 kbytes of EB13 are to be erased. 4 EB12 0 R/W When this bit is set to 1, 64 kbytes of EB12 are to be erased. 3 EB11 0 R/W When this bit is set to 1, 64 kbytes of EB11 are to be erased. 2 EB10 0 R/W When this bit is set to 1, 64 kbytes of EB10 are to be erased.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.6 On-Board Programming Modes In an on-board programming mode, programming, erasing, and verification for the on-chip flash memory can be performed. There are two on-board programming modes: boot mode and user program mode. Table 19.4 shows how to select boot mode. User program mode can be selected by setting the control bits by software. For a diagram that shows mode transitions of flash memory, see figure 19.2. Table 19.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 3. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 19.7, Flash Memory Programming/Erasing. 4. Before branching to the programming control program, the chip terminates transfer operations by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) Host Operation Communication Contents Processing Contents Bit rate adjustment Boot mode initiation Item Table 19.5 Boot Mode Operation LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. H'00, H'00 . . . H'00 H'00 Transmits data H'55 when data H'00 is received error-free. • Measures low-level period of receive data H'00.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 8 to 25 MHz 9,600 bps 8 to 25 MHz 19.6.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase program.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.7 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 8. The maximum number of repetitions of the program/program-verify sequence to the same bit (N) must not be exceeded. Start of programming Write pulse application subroutine Write pulse application Start Enable WDT Set SWE bit in FLMCR1 Wait (x) μs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU bit in FLMCR1 Wait (y) μs *6 Perform programming in the erased state.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.7.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.8 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time.
Section 19 Flash Memory (0.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.8 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or standby mode.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is forcibly aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, since PV and EV bit setting is enabled, and a transition can be made to verify mode. The error protection state can be canceled by a reset or in hardware standby mode. 19.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 19.11 Usage Notes Precautions concerning the use of on-board programming mode, and programmer mode are summarized below. 1. Use the specified voltages and timing for programming and erasing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A).
Section 19 Flash Memory (0.35-μm F-ZTAT Version) 8. Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. 9. Apply the reset signal after the SWE, bit is cleared during its operation. The reset signal is applied at least 100 µs after the SWE bit has been cleared. Rev.6.00 Mar.
Section 19 Flash Memory (0.
Section 19 Flash Memory (0.
Section 19 Flash Memory (0.35-μm F-ZTAT Version) Rev.6.00 Mar.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Section 20 Flash Memory (0.18-μm F-ZTAT Version) The flash memory has the following features. Figure 20.1 shows a block diagram of the flash memory. 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • Three on-board programming modes and one off-board programming mode ⎯ Boot mode This mode is a program mode that uses an on-chip SCI interface. The user MAT and user boot MAT can be programmed. This mode can automatically adjust the bit rate between host and this LSI. ⎯ User program mode The user MAT can be programmed by using the optional interface.
Section 20 Flash Memory (0.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.1.1 Operating Mode When each mode pin and the FWE pin are set in the reset state and reset start is performed, the microcomputer enters each operating mode as shown in figure 20.2. • Flash memory cannot be read, programmed, or erased in ROM invalid mode. • Flash memory can be read in user mode, but cannot be programmed or erased. • Flash memory can be read, programmed, or erased on the board only in user program mode, user boot mode, and boot mode.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.1.2 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and PROM mode is shown in table 20.1. Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.1.3 Flash MAT Configuration This LSI’s flash memory is configured by the 256-kbyte/384-kbyte/512-kbyte user MAT and 8kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes if it is in ROM valid mode.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.1.4 Block Division The user MAT is divided into 64 kbytes (seven blocks), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 20.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB15 is specified when erasing.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.1.5 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. An overview of the procedure is given as follows. For details, see section 20.4.2, User Program Mode. Start user procedure program for programming/erasing.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 2. Download of on-chip program The on-chip program is automatically downloaded by setting the SCO bit in the flash key register (FKEY) and the flash control register (FCCS) of the programming/erasing interface register. The flash memory is replaced to the embedded program storage area when downloading.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.2 Input/Output Pins Table 20.2 shows the flash memory pin configuration. Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • Flash program and erase frequency control (FPEFEQ) • Flash vector address control register (FVACR) There are several operating modes for accessing flash memory, for example, read mode/program mode. There are two memory MATs: user MAT and user boot MAT. The dedicated registers/parameters are allocated for each operating mode and MAT selection. The correspondence of operating modes and registers/parameters for use is shown in table 20.3. Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.3.1 Programming/Erasing Interface Register The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not initialized in software standby mode.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W 4 FLER 0 R Description Flash Memory Error Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. This bit is initialized at transition to a power-on reset or hardware standby mode. When FLER is set to 1, high voltage is applied to the internal flash memory.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 0 SCO 0 (R)/W Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM specified by FTDAR. In order to set this bit to 1, H'A5 must be written to FKEY, and this operation must be executed in the on-chip RAM.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit Bit Name Initial Value R/W Description 7 to 1 ⎯ All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 PPVS 0 R/W Program Pulse Verify Selects the programming program.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download on-chip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0 0/1* 0 0/1* 0 0/1* 0 R/W R/W R/W R/W R/W R/W R/W R/W MAT Select These bits are in user-MAT selection state when the value other than H'AA is written and in user-boot-MAT selection state when H'AA is written.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • Flash Transfer Destination Address Register (FTDAR) FTDAR is a register that specify the address to download an on-chip program. This register must be specified before setting the SCO bit in FCCS to 1. Bit Bit Name Initial Value R/W Description 7 TDER 0 R/W Transfer Destination Address Setting Error This bit is set to 1 when the address specified by bits TDA6 to TDA0, which is the start address to download an on-chip program, is over the range.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.3.2 Programming/Erasing Interface Parameter The programming/erasing interface parameter specifies the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a power-on reset or in hardware standby mode.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ ⎯ ⎯ Unused Return 0 2 SS ⎯ R/W Source Select Error Detect Only one type for the on-chip program which can be downloaded can be specified. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, error is occurred.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (b) Flash user branch address setting parameter (FUBRA: general register ER1 of CPU) This parameter sets the user branch destination address. A specified user program can be used to perform programming or erasing of processing units of predetermined size. When using the user branch function, set the flash user branch enable bits in FPEFEQ to H'AAFF in addition to the settings in this register.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (c) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the initialization result. Bit Bit Name Initial Value R/W Description 7 to 2 ⎯ ⎯ ⎯ Unused Return 0 1 FQ ⎯ R/W Frequency Error Detect Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU) This parameter stores the start address of the programming destination on the user MAT. When the address in the area other than flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (c) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the program processing result. Bit Bit Name Initial Value R/W Description 7 ⎯ ⎯ ⎯ Unused Return 0. 6 MD ⎯ R/W Programming Mode Related Setting Error Detect Returns the check result that the error protection state is not entered. When the error protection state is entered, 1 is written to this bit.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 2 WD ⎯ R/W Write Data Address Detect When the address in the flash memory area is specified as the start address of the storage destination of the program data, an error occurs.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block number 0 to 15. For details on the erasing processing procedure, see section 20.4.2, User Program Mode.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (b) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter returns value of the erasing processing result. Bit Bit Name Initial Value R/W Description 7 ⎯ ⎯ ⎯ Unused Return 0. 6 MD Programming Mode Related Setting Error Detect Returns the check result of whether the error protection state is entered. The error protection state is entered, 1 is written to this bit.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Bit Bit Name Initial Value R/W Description 3 EB ⎯ R/W Erase Block Select Error Detect Returns the check result whether the specified eraseblock number is in the block range of the user MAT. 0: Setting of erase-block number is normal 1: Setting of erase-block number is abnormal 2, 1 ⎯ ⎯ ⎯ Unused Return 0. 0 SF ⎯ R/W Success/Fail Indicates whether the erasing processing is ended normally or not.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.3.3 Flash Vector Address Control Register (FVACR) FVACR modifies the space from which the vector table data of the NMI interrupts is read. Normally the vector table data is read from the address spaces from H'00001C to H'00001F. However, the vector table can be read from the on-chip RAM by the FVACR setting. FVACR is initialized to H'00 at a power-on reset or in hardware standby mode.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.4 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user programming mode, user boot mode, and boot mode. For details of the pin setting for entering each mode, see table 20.5.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) This LSI Host Boot Control command, program data programming tool and program data Reply response Control command, analysis execution software (on-chip) Flash memory RxD1 On-chip SCI1 TxD1 On-chip RAM Figure 20.6 System Configuration in Boot Mode (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI Bit Rate of Host System Clock Frequency 9,600 bps 8 to 25 MHz 19,200 bps 8 to 25 MHz (2) State Transition Diagram The overview of the state transition diagram after boot mode is initiated is shown in figure 20.8. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) ⎯ When the erasure preparation notice is received, the state for waiting erase-block data is entered. The erase-block number must be transmitted following the erasing command. When the erasure is finished, the erase-block number must be set to H'FF and transmitted. Then the state for waiting erase-block data is returned to the state for waiting programming/erasing command.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (Bit rate adjustment) H'00.......
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.4.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 20.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby must not be executed.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (1) On-chip RAM Address Map when Programming/Erasing Is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so that these parts do not overlap. Figure 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 20.11. 1. Disable interrupts and bus master operation other than CPU Set FKEY to H'A5 2. Set FKEY to H'5A 10. Set SCO to 1 and execute download 3. Set parameters to ER1 and ER0 (FMPAR and FMPDR) 11. Clear FKEY to 0 4. Programming JSR FTDAR setting + 16 12.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for Programming Data. The following description assumes the area to be programmed on the user MAT is erased and program data is prepared in the consecutive area. When erasing is not executed, erasing is executed before writing.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) ⎯ After the selection condition of the download program and the FTDAR setting are checked, the transfer processing to the on-chip RAM specified by FTDAR is executed. ⎯ The SCO bits in FPCS, FECS, and FCCS are cleared to 0. ⎯ The return value is set to the DPFR parameter. ⎯ After the on-chip program storage area is returned to the user-MAT space, the user procedure program is returned. The notes on download are as follows.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) ⎯ If the value of the DPFR parameter is different from before downloading, check the SS bit (bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program selection and FKEY setting were normal, respectively. 6. The operating frequency and user branch destination are set to the FPEFEQ and FUBRA parameters for initialization. ⎯ The current frequency of the CPU clock is set to the FPEFEQ parameter (general register ER0).
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 9. All interrupts and the use of a bus master other than the CPU are prohibited. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during this time, the voltage for more than the specified time will be applied and flash memory may be damaged.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) ⎯ The general registers other than ER0, ER1 are held in the programming program. ⎯ R0L is a return value of the FPFR parameter. ⎯ Since the stack area is used in the programming program, a stack area of a maximum 128 bytes must be allocated in RAM 13. The return value in the programming program, FPFR (general register R0L) is determined. 14. Determine whether programming of the necessary data has finished.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) ⎯ Programming finished processing should be poerformed immediately after programming of the necessary data has completed. Caution is necessary because if an operation such as initialization processing, internal program downloading, rewriting an area of RAM that is a download destination, or MAT switching is performed before programming finished processing, programming will not take place correctly.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 20.12. Start erasing procedure program a Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 and execute download Set FEBS parameter 2. Erasing JSR FTDAR setting + 16 3. Clear FKEY to 0 DPFR = 0? Yes 4.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) A single divided block is erased by one erasing processing. For block divisions, refer to figure 20.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. 1. Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT erasure has completed, secure a reset period (period of RES = 0) that is at least as long as normal 100 μs. 20.4.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings than those in user program mode or boot mode.
Section 20 Flash Memory (0.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) programmed, the procedure program must be located in an area other than flash memory. After programming completes, switch the MATs again to return to the first state. MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g.
Section 20 Flash Memory (0.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for Programming Data. 20.4.4 Procedure Program and Storable Area for Programming Data In the descriptions in the previous section, the programming/erasing procedure programs and storable areas for program data are assumed to be in the on-chip RAM.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 8. When the data storable area indicated by programming parameter FMPDR is within the flash memory area, an error will occur even when the data stored is normal. Therefore, the data should be transferred to the on-chip RAM to place the address that FMPDR indicates in an area other than the flash memory. In consideration of these conditions, there are three factors; operating mode, the bank structure of the user MAT, and operations.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Storable /Executable Area On-chip RAM Item Target Flash Memory Execution of Programming × Determination of Program Result × Operation for Program Error × Operation for FKEY Clear × Note: * Selected MAT External Space (Expanded Mode) User MAT Embedded Program Storage Area × Transferring the data to the on-chip RAM enables this area to be used. Rev.6.00 Mar.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Storable /Executable Area Item On-chip RAM User MAT Operation for Erasure Error × Operation for FKEY Clear × Selected MAT External Space (Expanded Mode) User MAT Embedded Program Storage Area Rev.6.00 Mar.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Storable/Executable Area Item On-chip RAM User Boot MAT Operation for Writing H'5A to FKEY × Operation for Settings of Program Parameter × Execution of Programming × Determination of Program Result × Operation for Program Error Selected MAT External Space (Expanded Mode) User MAT User Boot MAT Embedded Program Storage Area × × *2 Operation for FKEY Clear × Switching MATs by FMATS × × Notes: 1.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Storable/Executable Area On-chip RAM Item User Boot MAT Operation for Settings of Erasure Parameter × Execution of Erasure × Determination of Erasure Result × Operation for Erasure Error ×* Operation for FKEY Clear × Switching MATs by FMATS × Note: * Selected MAT External Space (Expanded Mode) User MAT User Boot MAT Embedded Program Storage Area × × Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev.6.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.5 Protection There are two kinds of flash memory program/erase protection: hardware and software protection. 20.5.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of a on-chip program and initialization are possible.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.5.2 Software Protection Software protection is set up by disabling the downloading of on-chip programs for programming and erasing or by means of a key code register. Table 20.10 Software Protection Function to be Protected Item Description Protection by the SCO bit • The program/erase-protected state is entered by clearing the SCO bit in FCCS which disables the downloading of the programming/erasing programs.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) The FLER bit is set in the following conditions: 1. When an interrupt such as NMI occurs during programming/erasing. 2. When the flash memory is read during programming/erasing (including a vector read or an instruction fetch). 3. When a SLEEP instruction (including software-standby mode) is executed during programming/erasing. 4. When a bus master other than the CPU such as the DMAC or DTC gets bus mastership during programming/erasing.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.6 Switching between User MAT and User Boot MAT It is possible to alternate between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or PROM mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.7 Programmer Mode Along with its on-board programming mode, this LSI also has a PROM mode as a further mode for the writing and erasing of programs and data. In the PROM mode, a general-purpose PROM programmer can freely be used to write programs to the on-chip ROM. Program/erase is possible on the user MAT and user boot MAT. The PROM programmer must support Renesas microcomputers with 512-kbyte flash memory as a device type.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) These boot program states are shown in figure 20.17. Reset Bit-rate-adjustment state Inquiry/response wait Response Inquiry Operations for inquiry and selection Transition to programming/erasing Operations for response Operations for erasing user MATs and user boot MATs Programming/erasing wait Programming Erasing Operations for programming Checking Operations for erasing Operations for checking Figure 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Host Boot Program H'00 (30 times maximum) Measuring the 1-bit length H'00 (Completion of adjustment) H'55 H'E6 (Boot response) H'FF (error) Figure 20.18 Bit-Rate-Adjustment Sequence (3) Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These commands and responses are comprised of a single byte.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) One-byte command or one-byte response Command or response n-byte Command or n-byte response Data Size Checksum Command or response Error response Error code Error response 128-byte programming Address Data (n bytes) Command Memory read response Size Checksum Data Response Checksum Figure 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (4) Inquiry and Selection States The boot program returns information from the flash memory in response to the host’s inquiry commands and sets the device code, clock mode, and bit rate in response to the host’s selection command. Inquiry and selection commands are listed below. Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40).
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (b) Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • Area-last address (four byte): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. • SUM (one byte): Checksum (i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Error Response H'BF ERROR • Error response, H'BF, (one byte): Error response to selection of new bit rate • ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value(N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency (φ) and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (6) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (9) Programming/Erasing State A programming selection command makes the boot program select the programming method, an 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/erasing commands are listed below. Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • Programming Programming is executed by a programming-selection command and an 128-byte programming command. Firstly, the host should send the programming-selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. 1. User boot MAT programming selection 2.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Host Boot program Programming selection (H'42, H'43) Transfer of the programming program ACK 128-byte programming (address, data) Repeat Programming ACK 128-byte programming (H'FFFFFFFF) ACK Figure 20.21 Programming Sequence (a) User boot MAT programming selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Response H'06 • Response, H'06, (one byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower byte of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Host Boot program Preparation for erasure (H'48) Transfer of erasure program ACK Erasure (Erasure block number) Repeat Erasure ACK Erasure (H'FF) ACK Figure 20.22 Erasure Sequence (a) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (b) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size Block number SUM • Command, H'58, (one byte): Erasure • Size (one byte): The number of bytes that represents the erasure block number This is fixed to 1.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (11) Memory read The boot program will return the data in the specified address. Command H'52 Size Area Read address Read size SUM • Command: H'52 (1 byte): Memory read • Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) • Area (1 byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) Response H'5A Size Checksum of user boot program SUM • Response, H'5A, (one byte): Response to the sum check of user-boot program • Size (one byte): The number of bytes that represents the checksum This is fixed to 4. • Checksum of user boot program (four bytes): Checksum of user boot MATs The total of the data is obtained in byte units.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) (15) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D • Command, H'4D, (one byte): Blank check for user MATs Response H'06 • Response, H'06, (one byte): Response to the blank check for user boot MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) • ERROR (one byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. Table 20.
Section 20 Flash Memory (0.18-μm F-ZTAT Version) 20.9 Usage Notes 1. Download time of on-chip program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock frequency is 34 MHz, the download for each program takes approximately 60 μs at maximum. 2.
Section 21 Mask ROM Section 21 Mask ROM H8S/2635 has 256 kbytes of mask ROM. The on-chip ROM is connected to the CPU, data transfer controller (DTC), and DMA controller (DMAC) with a 16-bit data bus. The on-chip ROM can be accessed by the CPU, DTC, and DMAC in 8 or 16-bit units. The data in the on-chip ROM can always be accessed in one state. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000001 H'000002 H'000003 H'03FFFE H'03FFFF Figure 21.
Section 21 Mask ROM Rev.6.00 Mar.
Section 22 Clock Pulse Generator Section 22 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and internal clocks. The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider. Figure 22.1 shows a block diagram of the clock pulse generator.
Section 22 Clock Pulse Generator 22.1.1 System Clock Control Register (SCKCR) SCKCR controls φ clock output and selects operation when the frequency multiplication factor used by the PLL circuit is changed, and the division ratio used by the divider. Bit Bit Name Initial Value R/W Description 7 PSTOP 0 R/W φ Clock Output Disable Controls φ output.
Section 22 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 2 1 0 SCK2 SCK1 SCK0 0 0 0 R/W R/W R/W System Clock Select 2 to 0 Select the division ratio. 000: 1/1 001: 1/2 010: 1/4 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 11×: Setting prohibited Legend: ×: Don’t care 22.1.2 PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the PLL circuit.
Section 22 Clock Pulse Generator 22.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 22.2.1 Connecting a Crystal Oscillator A crystal oscillator can be connected as shown in the example in figure 22.2. Select the damping resistance Rd according to table 22.1. An AT-cut parallel-resonance type should be used. When a clock is supplied with a crystal resonator connected, the frequency of the crystal resonator should be 8 MHz to 25 MHz.
Section 22 Clock Pulse Generator Table 22.2 Crystal Oscillator Characteristics Frequency (MHz) 8 12 16 20 25 RS max (Ω) 80 60 50 40 40 C0 max (pF) 7 7 7 7 7 22.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 22.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode. Table 22.
Section 22 Clock Pulse Generator Table 22.3 External Clock Input Conditions VCC = 3.0 V to 3.6 V Item Symbol Min Max Unit Test Conditions External clock input low pulse width tEXL 15 — ns Figure 22.5 External clock input high pulse width tEXH 15 — ns External clock rise time tEXr — 5 ns External clock fall time tEXf — 5 ns Clock low pulse width tCL 0.4 0.6 tcyc Clock high pulse width tCH 0.4 0.6 tcyc tEXH tEXL EXTAL VCC × 0.5 tEXr tEXf Figure 22.
Section 22 Clock Pulse Generator 2. A value is set in bits STS3 to STS0 to give the specified transition time. 3. The target value is set in bits STC1 and STC0, and a transition is made to software standby mode. 4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. 5. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS3 to STS0. 6.
Section 22 Clock Pulse Generator 22.5.2 Notes on Oscillator Since various characteristics related to the oscillator are closely linked to the user’s board design, thorough evaluation is necessary on the user’s part, using the oscillator connection examples shown in this section as a guide. As the oscillator circuit ratings will depend on the floating capacitance of the oscillator and the mounting circuit, the ratings should be determined in consultation with the oscillator manufacturer.
Section 22 Clock Pulse Generator Rp: 200 PLLVCC CPB: 0.1 µF* PLLVSS VCC CB: 0.1 µF* VSS Note: * CB and CPB are laminated ceramic capacitors. Figure 22.7 Recommended External Circuitry for PLL Circuit Rev.6.00 Mar.
Section 22 Clock Pulse Generator Rev.6.00 Mar.
Section 23 Power-Down Modes Section 23 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
Section 23 Power-Down Modes Table 23.
Section 23 Power-Down Modes In module stop mode, only modules for which a stop setting has been made are halted (reset or retained). 1. The active or halted state can be selected by means of the MSTP0 bit in MSTPCR. 2. TDR, SSR, and RDR are halted (reset) and other registers are halted (retained). 3. BC2 to BC0 are halted (reset) and other registers are halted (retained).
Section 23 Power-Down Modes 23.1 Register Descriptions The registers relating to the power-down mode are shown below. For details on the system clock control register (SCKCR), refer to section 22.1.1, System Clock Control Register (SCKCR).
Section 23 Power-Down Modes Bit Bit Name Initial Value R/W Description 5, 4 — All 0 — Reserved These bits are always read as 0. The initial value should not be changed. 3 2 1 0 STS3 STS2 STS1 STS0 1 1 1 1 R/W R/W R/W R/W Standby Timer Select 3 to 0 These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 23.
Section 23 Power-Down Modes 23.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode.
Section 23 Power-Down Modes 23.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) EXMSTPCR performs all-module-clocks-stop mode control with MSTPCR. When entering all-module-clocks-stop mode, set EXMSTPCR to H’FFFF. Otherwise, set EXMSTPCR to H’FFFD. • EXMSTPCRH Bit Bit Name Initial Value R/W Module 15 to 12 — All 1 R/W Reserved 11 MSTP27 1 R/W — 10 MSTP26 1 R/W — 9 MSTP25 1 R/W — 8 MSTP24 1 R/W — • Read/write is enabled.
Section 23 Power-Down Modes 23.2 Operation 23.2.1 Clock Division Mode When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and on-chip peripheral functions all operate on the operating clock (1/2 or 1/4) specified by bits SCK2 to SCK0. Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0.
Section 23 Power-Down Modes When the STBY pin level is driven low, a transition is made to hardware standby mode. 23.2.3 Software Standby Mode Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
Section 23 Power-Down Modes Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS3 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time. Table 23.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0. Using an External Clock: A PLL circuit stabilization time is necessary. Refer to table 23.2 to set the wait time. Table 23.
Section 23 Power-Down Modes Software Standby Mode Application Example: Figure 23.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin.
Section 23 Power-Down Modes 23.2.4 Hardware Standby Mode Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state.
Section 23 Power-Down Modes Hardware Standby Mode Timing when Power Is Supplied (Only H8S/2368 0.18 μm F-ZTAT Group): When entering hardware standby mode immediately after the power is supplied, the RES signal must be driven low for a given period with retaining the STBY signal high. After the RES signal is canceled, drive the STBY signal low. (1) Power supply RES (2) Reset period STBY (3) Hardware standby mode Figure 23.4 Hardware Standby Mode Timing when Power Is Supplied 23.2.
Section 23 Power-Down Modes 23.2.
Section 23 Power-Down Modes 23.4 Usage Notes 23.4.1 I/O Port Status In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 23.4.2 Current Dissipation during Oscillation Stabilization Standby Period Current dissipation increases during the oscillation stabilization standby period. 23.4.
Section 23 Power-Down Modes 23.4.6 Notes on Clock Division Mode The following points should be noted in clock division mode. • Select the clock division ratio specified by the SCK2 to SCK0 bits so that the frequency of φ is within the operation guaranteed range of clock cycle time (tcyc) shown in the Electrical Characteristics. In other words, the range of φ must be specified to 8 MHz (min.); outside of this range (φ < 8 MHz) must be prevented. • All the on-chip peripheral modules operate on the φ.
Section 24 List of Registers Section 24 List of Registers The address list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) ⎯ Registers are listed from the lower allocation addresses. ⎯ Registers are classified by functional modules. ⎯ The access size is indicated. 2.
Section 24 List of Registers 24.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers Register Name Abbreviation Bit No.
Section 24 List of Registers 24.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16- or 32-bit registers are shown as 2 or 4 lines.
Section 24 List of Registers Register Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SEMR_2 — — — — ABCS ACS2 ACS1 ACS0 SCI_2 Smart card interface 2 IPRA — IPRA14 IPRA13 IPRA12 — IPRA10 IPRA9 IPRA8 INT — IPRA6 IPRA5 IPRA4 — IPRA2 IPRA1 IPRA0 IPRB — IPRB14 IPRB13 IPRB12 — IPRB10 IPRB9 IPRB8 — IPRB6 IPRB5 IPRB4 — IPRB2 IPRB1 IPRB0 — IPRC14 IPRC13 IPRC12 — IPRC10 IPRC9 IPRC8 — IPRC6 IPRC5 IPRC4 — IPRC2 IPRC1 IPRC0 — IPRD14 IPR
Section 24 List of Registers Register Bit 7 Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR P3DDR — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR P5DDR — — — P8DDR — — P85DDR — PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR
Section 24 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 4 SMR_4* 5 * SMR_4 Bit 3 Bit 2 Bit 1 Bit 0 Module C/A CHR PE O/E GM BLK PE O/E STOP MP CKS1 CKS0 BCP1 BCP0 CKS1 CKS0 SCI_4 Smart card interface 4 BRR_4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_4 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ORER FER PER TEND MPB MPBT SSR_4* 5 SSR_4* TDRE RDRF TDRE RDRF ORER ERS PER TEND MPB MPBT RDR_4
Section 24 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCNT_4 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TCR_5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_5 — — — — MD3
Section 24 List of Registers Register Name Bit 7 Bit 6 BCR BRLE BREQ0E — DRAMCR DRACCR REFCR Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IDLC ICIS1 ICIS0 WDBE WAITE BSC — — — — — ICIS2 — — OEE RAST — CAST — RMTS2 RMTS1 RMTS0 BE RCDM DDS — — MXC2 MXC1 MXC0 DRMI — TPC1 TPC0 — — RCD1 RCD0 CMF CMIE RCW1 RCW0 — RTCK2 RTCK1 RTCK0 RFSHE CBRM RLW1 RLW0 SLFRF TPCS2 TPCS1 TPCS0 RTCNT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RTCOR Bit7 Bit6
Section 24 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ETCR_1A Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 DMAC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MAR_1BH MAR_1BL IOARV1B ETCR_1B — — — — — — — — Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4
Section 24 List of Registers Register Name Bit 7 Bit 6 DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 DTC INTCR — — INTM1 INTM0 NMIEG — — — IER Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INT — — — — — — — — IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E — — — — — — — — IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F SBYCR SSBY OPE — — STS3 STS2 STS1 STS0 SCKCR PSTOP — — — STCS SCK2 SCK1 SCK0 SYSCR — — — — FLSHE —
Section 24 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORT PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTG — PG6 PG5 PG4 PG3 PG2 PG1 PG0 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR P2DR P27
Section 24 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module 4 SMR_1* 5 * SMR_1 C/A GM CHR BLK PE PE O/E O/E STOP BCP1 MP BCP0 CKS1 OKS1 CKS0 OKS0 BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCI_1, Smart card interface_1 SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 4 SSR_1* 5 SSR_1* TDRE TDRE RDRF RDRF ORER ORER FER ERS PER PER TEND TEND MPB MPB MPBT MPBT RDR_1 Bit7 Bit6
Section 24 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADCSR ADF ADIE ADST — CH3 CH2 CH1 CH0 A/D ADCR TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 — — DADR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DACR23 DAOE3 DAOE2 DAE — — — — — TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_0 TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_1 TCSR_0 CMFB CM
Section 24 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_0 TMDR_0 — — BFB BFA MD3 MD2 MD1 MD0 TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA TSR_0 — — — TCFV TGFD TGFC TGFB TGFA TCNT_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 B
Section 24 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2 TMDR_2 — — — — MD3 MD2 MD1 MD0 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_2 TTGE — TCIEU TCIEV — — TGIEB TGIEA TSR_2 TCFD — TCFU TCFV — — TGFB TGFA TCNT_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit15 Bit14 Bit13 Bit12 Bit11
Section 24 List of Registers 24.
Section 24 List of Registers Register Name Reset HighSpeed IPRG Initialized — Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module — — INT — — — Initialized IPRH Initialized — — — — — — Initialized IPRI Initialized — — — — — — Initialized IPRJ Initialized — — — — — — Initialized IPRK Initialized — — — — — — Initialized ITSR Initialized — — — — — — Initialized SSIER Initialized — — — — — — Initialized IS
Section 24 List of Registers Register Name Reset SMR_3 HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module Initialized — — — — — — Initialized SCI_3 BRR_3 Initialized — — — — — — Initialized SCR_3 Initialized — — — — — — Initialized TDR_3 Initialized — — — Initialized Initialized Initialized Initialized SSR_3 Initialized — — — Initialized Initialized Initialized Initialized RDR_3 Initialized — — — Initialize
Section 24 List of Registers Register Name Reset TCNT_4 HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module Initialized — — — — — — Initialized TPU_4 TGRA_4 Initialized — — — — — — Initialized TGRB_4 Initialized — — — — — — Initialized TCR_5 Initialized — — — — — — Initialized TMDR_5 Initialized — — — — — — Initialized TIOR_5 Initialized — — — — — — Initialized TIER_5 Initialized — — — — — — I
Section 24 List of Registers Register Name Reset MAR_0AH HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module Initialized — — — — — — Initialized DMAC MAR_0AL Initialized — — — — — — Initialized IOAR_0A Initialized — — — — — — Initialized ETCR_0A Initialized — — — — — — Initialized MAR_0BH Initialized — — — — — — Initialized MAR_0BL Initialized — — — — — — Initialized IOAR_0B Initialized — — — —
Section 24 List of Registers Register Name Reset DTVECH DTVECR HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module Initialized — — — — — — Initialized DTC Initialized — — — — — — Initialized INTCR Initialized — — — — — — Initialized IER Initialized — — — — — — Initialized ISR Initialized — — — — — — Initialized SBYCR Initialized — — — — — — Initialized SCKCR Initialized — — — — — — Initialized
Section 24 List of Registers Register Name Reset HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module PORTA — — — — — — — — PORT PORTB — — — — — — — — PORTC — — — — — — — — PORTD — — — — — — — — PORTE — — — — — — — — PORTF — — — — — — — — PORTG — — — — — — — — P1DR Initialized — — — — — — Initialized P2DR Initialized — — — — — — Initialized P3DR Initialized — — — —
Section 24 List of Registers Register Name Reset SMR_1 HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module Initialized — — — — — — Initialized SCI_1 BRR_1 Initialized — — — — — — Initialized SCR_1 Initialized — — — — — — Initialized TDR_1 Initialized — — — Initialized Initialized Initialized Initialized SSR_1 Initialized — — — Initialized Initialized Initialized Initialized RDR_1 Initialized — — — Initialize
Section 24 List of Registers Register Name Reset TCR_0 HighSpeed Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Initialized — — — — — — Initialized TCR_1 Initialized — — — — — — Initialized TCSR_0 Initialized — — — — — — Initialized TCSR_1 Initialized — — — — — — Initialized TCORA_0 Initialized — — — — — — Initialized TCORA_1 Initialized — — — — — — Initialized TCORB_0 Initialized — — — — — — Initialized T
Section 24 List of Registers Register Name Reset TCR_0 Clock Module Division Sleep Stop All Module Software Hardware Clock Stop Standby Standby Module Initialized — — — — — — Initialized TPU_0 TMDR_0 Initialized — — — — — — Initialized TIORH_0 Initialized — — — — — — Initialized TIORL_0 Initialized — — — — — — Initialized TIER_0 Initialized — — — — — — Initialized TSR_0 Initialized — — — — — — Initialized TCNT_0 Initialized — — — — — — Initialized
Section 25 Electrical Characteristics Section 25 Electrical Characteristics 25.1 Electrical Characteristics of Masked ROM and ROMless Versions 25.1.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +4.0 V PLLVCC Input voltage (except ports 4, 9) Vin –0.3 to VCC +0.3 V Input voltage (ports 4, 9) Vin –0.3 to AVCC +0.3 V Reference power supply voltage Vref –0.3 to AVCC +0.
Section 25 Electrical Characteristics 25.1.2 DC Characteristics Table 25.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Typ Max Test Unit Conditions — — V — VCC × 0.7 V — — V VCC × 0.9 — VCC +0.3 V RES, NMI, EMLE VCC × 0.9 — VCC +0.3 V Item Symbol Min Schmitt Ports 1, 2, and 4*2, VT– VCC × 0.
Section 25 Electrical Characteristics Table 25.3 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Symbol Min Typ Max Test Unit Conditions |Iin| — — 10.0 μA STBY, NMI, MD2 to MD0 — — 1.0 μA Ports 4 and 9 — — 1.0 μA Vin = 0.5 to AVCC –0.5 V | ITSI | — — 1.0 μA Vin = 0.5 to VCC –0.5 V –Ip 10 — 300 μA VCC = 3.
Section 25 Electrical Characteristics Item Reference power supply current During A/D and D/A conversion Min Typ AICC — 2.0 3.5 (3.0 V) mA — 0.01 5.0 μA 2.0 — — V Idle RAM standby voltage Test Unit Conditions Symbol VRAM Max Notes: 1. When the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current dissipation values are for VIHmin = VCC – 0.2 V and VILmax = 0.
Section 25 Electrical Characteristics 25.1.3 AC Characteristics 3V RL C = 50 pF: ports A to G C = 30 pF: ports 1 to 3, P50 to P53, port 8 LSI output pin C RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement level: 1.5 V (VCC = 3.0 V to 3.6 V) RH Figure 25.1 Output Load Circuit Rev.6.00 Mar.
Section 25 Electrical Characteristics (1) Clock Timing Table 25.5 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 30.3 125 ns Figure 25.2 Clock pulse high width tCH 10 — ns Figure 25.
Section 25 Electrical Characteristics EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 25.3 Oscillation Stabilization Timing (1) Oscillator φ NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 SLEEP instruction Figure 25.3 Oscillation Stabilization Timing (2) Rev.6.00 Mar.
Section 25 Electrical Characteristics (2) Control Signal Timing Table 25.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 — ns Figure 25.
Section 25 Electrical Characteristics φ tNMIS tNMIH NMI tNMIW tIRQW IRQi (i = 0 to 7)* tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * Necessary for SSIER setting to clear software standby mode. Figure 25.5 Interrupt Input Timing Rev.6.00 Mar.
Section 25 Electrical Characteristics (3) Bus Timing Table 25.7 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Address delay time tAD — 20 ns Address setup time 1 tAS1 0.5 × tcyc –13 — ns Figures 25.6 to 25.19 Address setup time 2 tAS2 1.
Section 25 Electrical Characteristics Item Symbol Min Max Unit Test Conditions Address read data access time 1 tAA1 — 1.0 × tcyc –20 ns Address read data access time 2 tAA2 — 1.5 × tcyc –20 ns Figures 25.6 to 25.19 Address read data access time 3 tAA3 — 2.0 × tcyc –20 ns Address read data access time 4 tAA4 — 2.5 × tcyc –20 ns Address read data access time 5 tAA5 — 3.0 × tcyc –20 ns Rev.6.00 Mar.
Section 25 Electrical Characteristics Table 25.8 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions WR delay time 1 tWRD1 — 15 ns WR delay time 2 tWRD2 — 15 ns Figures 25.6 to 25.19 WR pulse width 1 tWSW1 1.0 × tcyc –13 — ns WR pulse width 2 tWSW2 1.
Section 25 Electrical Characteristics Item Symbol Min Max Unit Test Conditions Precharge time 1 tPCH1 1.0 × tcyc –20 — ns Precharge time 2 tPCH2 1.5 × tcyc –20 — ns Figures 25.6 to 25.19 Self-refresh precharge time 1 tRPS1 2.5 × tcyc –20 — ns Self-refresh precharge time 2 tRPS2 3.
Section 25 Electrical Characteristics T1 T2 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC5 tAA2 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 tAA3 D15 to D0 tAS1 tWRD2 tWRD2 tAH1 HWR, LWR tWDD Write tWSW1 tWDH1 D15 to D0 tDACD1 DACK0, DACK1 Figure 25.6 Basic Bus Timing: Two-State Access Rev.6.00 Mar.
Section 25 Electrical Characteristics T2 T1 T3 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 tAA4 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tRDS2 tAC4 tRDH2 tAA5 D15 to D0 tAS2 tAH1 tWRD1 HWR, LWR tWDS1 tWDD Write tWRD2 tWSW2 tWDH1 D15 to D0 tDACD2 tDACD1 DACK0, DACK1 Figure 25.7 Basic Bus Timing: Three-State Access Rev.6.00 Mar.
Section 25 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD Read (RDNn = 1) D15 to D0 RD Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 WAIT Figure 25.8 Basic Bus Timing: Three-State Access, One Wait Rev.6.00 Mar.
Section 25 Electrical Characteristics T1 Th T2 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS3 tAH3 tRSD1 tRSD1 RD Read (RDNn = 1) tAC5 tRDS1 tRDH1 tRSD1 tRSD2 D15 to D0 tAS3 tAH2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 D15 to D0 tAS3 tWRD2 tWRD2 tAH3 HWR, LWR tWDD Write tWDS2 tWSW1 tWDH3 D15 to D0 tDACD1 tDACD2 DACK0, DACK1 Figure 25.9 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) Rev.6.00 Mar.
Section 25 Electrical Characteristics Th T1 T2 T3 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS3 tRSD1 tAH3 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 D15 to D0 tAS3 tAH2 tRSD2 tRSD1 RD Read (RDNn = 0) tRDS2 tRDH2 tAC4 D15 to D0 tAS4 tAH3 tWRD1 HWR, LWR tWDS3 tWDD Write tWRD2 tWSW2 tWDH3 D15 to D0 tDACD1 tDACD2 DACK0, DACK1 Figure 25.10 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) Rev.6.00 Mar.
Section 25 Electrical Characteristics T1 T1 T2 T1 φ A23 to A6, A0 tAD A5 to A1 CS1, CS0 AS tRSD2 RD tAA1 tRDS2 tRDH2 Read D15 to D0 HWR, LWR Figure 25.11 Burst ROM Access Timing: One-State Burst Access Rev.6.00 Mar.
Section 25 Electrical Characteristics T1 T2 T3 T1 T2 φ A23 to A6, A0 tAD A5 to A1 CS1, CS0 tAH1 tAS1 tASD AS tASD tRSD2 RD Read tAA3 D15 to D0 HWR, LWR Figure 25.12 Burst ROM Access Timing: Two-State Burst Access Rev.6.00 Mar.
Section 25 Electrical Characteristics Tr Tp Tc1 Tc2 φ tAD tAD A23 to A0 tAS3 RAS3, RAS2 tCSD3 tAH1 tCSD2 tAS2 tPCH2 tAH2 tCASD1 tCASD1 UCAS tCASW1 LCAS tOED1 tOED1 tAC1 OE, RD Read HWR tAA3 tRDS2 tRDH2 tAC4 D15 to D0 OE, RD tWRD2 Write tWCS1 tWCH1 tWRD2 HWR tWDD tWDS1 tWDH2 D15 to D0 AS tDACD1 tDACD2 DACK0, DACK1 Notes: DACK timing: when DDS = 0 RAS timing: when RAST = 0 Figure 25.13 DRAM Access Timing: Two-State Access Rev.6.00 Mar.
Section 25 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp tWTS tWTH tWTS tWTH Tc2 φ A23 to A0 RAS3, RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE, RD Write HWR D15 to D0 AS WAIT DACK0, DACK1 Notes: DACK timing: when DDS = 0 RAS timing: when RAST = 0 Tcw : Tcwp: Wait cycle inserted by programmable wait function Wait cycle inserted by pin wait function Figure 25.14 DRAM Access Timing: Two-State Access, One Wait Rev.6.00 Mar.
Section 25 Electrical Characteristics Tp Tr Tc1 Tc2 Tc1 Tc2 φ A23 to A0 RAS3, RAS2 tCPW1 UCAS LCAS OE, RD Read HWR tAC3 D15 to D0 OE, RD Write tRCH HWR tRCS1 D15 to D0 AS tDACD1 tDACD2 DACK0, DACK1 Notes: DACK timing: when DDS = 1 RAS timing: when RAST = 1 Figure 25.15 DRAM Access Timing: Two-State Burst Access Rev.6.00 Mar.
Section 25 Electrical Characteristics Tp Tc1 Tr Tc2 Tc3 φ tAD tAD A23 to A0 tAS2 RAS3, RAS2 tCSD3 tAH2 tCSD2 tPCH1 tAS3 tAH3 tCASD1 tCASD2 UCAS tCASW2 LCAS tOED2 tOED1 tAC2 OE, RD Read HWR tAA5 tRDS2 tRDH2 tAC7 D15 to D0 OE, RD Write tWRD2 tWCS2 tWCH2 tWRD2 HWR tWDD tWDS2 tWDH3 D15 to D0 AS tDACD1 DACK0, DACK1 Notes: DACK timing: when DDS = 0 RAS timing: when RAST = 1 Figure 25.16 DRAM Access Timing: Three-State Access (RAST = 1) Rev.6.00 Mar.
Section 25 Electrical Characteristics Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ A23 to A0 RAS3, RAS2 tCPW2 UCAS LCAS OE, RD Read HWR tAC8 D15 to D0 OE, RD Write tRCH HWR tRCS2 D15 to D0 AS DACK0, DACK1 Notes: DACK timing: when DDS = 1 RAS timing: when RAST = 1 Figure 25.17 DRAM Access Timing: Three-State Burst Access Rev.6.00 Mar.
Section 25 Electrical Characteristics TRp TRc1 TRr TRc2 φ tCSD1 tCSD2 RAS3, RAS2 tCSR1 tCASD1 tCASD1 UCAS, LCAS OE Figure 25.18 CAS-Before-RAS Refresh Timing TRp TRrw TRr TRc1 TRcw TRc2 φ tCSD1 tCSD2 RAS3, RAS2 UCAS, LCAS tCSR2 tCASD1 OE Figure 25.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Rev.6.00 Mar.
Section 25 Electrical Characteristics Self-refresh TRp TRr TRc TRc DRAM access Tpsr Tp Tr φ tCSD2 tCSD2 RAS3, RAS2 tRPS2 tCASD1 tCASD1 UCAS, LCAS OE Figure 25.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Self-refresh TRp TRc TRr TRc Tpsr DRAM access Tp Tr φ tCSD2 RAS3, RAS2 tCASD1 tCSD2 tRPS1 tCASD1 UCAS, LCAS OE Figure 25.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) Rev.6.00 Mar.
Section 25 Electrical Characteristics φ tBREQS tBREQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0 (RAS3, RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 25.22 External Bus Release Timing φ BACK tBRQOD tBRQOD BREQO Figure 25.23 External Bus Request Output Timing Rev.6.00 Mar.
Section 25 Electrical Characteristics (4) DMAC Timing Table 25.9 DMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions DREQ setup time tDRQS 25 — ns Figure 25.27 DREQ hold time tDRQH 10 — TEND delay time tTED — 18 ns Figure 25.
Section 25 Electrical Characteristics T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 25.24 DMAC Single Address Transfer Timing: Two-State Access Rev.6.00 Mar.
Section 25 Electrical Characteristics T1 T3 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 25.25 DMAC Single Address Transfer Timing: Three-State Access T1 T2 or T3 φ tTED tTED TEND0, TEND1 Figure 25.26 DMAC TEND Output Timing Rev.6.00 Mar.
Section 25 Electrical Characteristics φ tDRQS tDRQH DREQ0, DREQ1 Figure 25.27 DMAC DREQ Input Timing (5) Timing of On-Chip Peripheral Modules Table 25.10 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Output data delay time tPWD — 40 ns Figure 25.
Section 25 Electrical Characteristics Item Symbol Min Max Unit Test Conditions WDT Overflow output delay time tWOVD — 40 ns Figure 25.35 SCI Input clock cycle tScyc 4 — tcyc Figure 25.36 6 — Asynchronous Synchronous Input clock pulse width tSCKW 0.4 0.6 tScyc Input clock rise time tSCKr — 1.5 tcyc Input clock fall time tSCKf — 1.
Section 25 Electrical Characteristics T1 T2 tPRS tPRH Ports 1 to 6, 8 and 9, A to G (read) tPWD Ports 1 to 3, 6, 8, P53 to P50, ports A to G (write) Figure 25.28 I/O Port Input/Output Timing tPOD PO15 to PO0 Figure 25.29 PPG Output Timing tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 25.30 TPU Input/Output Timing Rev.6.00 Mar.
Section 25 Electrical Characteristics tTCKS tTCKS TCLKA to TCLKD tTCKWH tTCKWL Figure 25.31 TPU Clock Input Timing tTMOD TMO0, TMO1 Figure 25.32 8-Bit Timer Output Timing tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 25.33 8-Bit Timer Clock Input Timing tTMRS TMRI0, TMRI1 Figure 25.34 8-Bit Timer Reset Input Timing Rev.6.00 Mar.
Section 25 Electrical Characteristics φ tWOVD tWOVD WDTOVF Figure 25.35 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK4 tScyc Figure 25.36 SCK Clock Input Timing SCK0 to SCK4 tTXD TxD0 to TxD4 (transmit data) tRXS tRXH RxD0 to RxD4 (receive data) Figure 25.37 SCI Input/Output Timing: Synchronous Mode φ tTRGS ADTRG Figure 25.38 A/D Converter External Trigger Input Timing Rev.6.00 Mar.
Section 25 Electrical Characteristics VIH SDA0 to SDA1 VIL tBUF tSTAH SCL0 to SCL1 P* tSCLH tSTAS S* tSf tSCLL tSCL tSP tSTOS Sr* tSr tSDAS tSDAH Note: * S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 25.39 I2C Bus Interface Input/Output Timing (Option) Rev.6.00 Mar.
Section 25 Electrical Characteristics 25.1.4 A/D Conversion Characteristics Table 25.11 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Min Typ Max Unit Resolution 10 10 10 Bit Conversion time 8.
Section 25 Electrical Characteristics 25.2 Electrical Characteristics of 0.35 μm F-ZTAT Version 25.2.1 Absolute Maximum Ratings Table 25.13 lists the absolute maximum ratings. Table 25.13 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +4.0 V PLLVCC Input voltage (except ports 4, 9) Vin –0.3 to VCC +0.3 V Input voltage (ports 4, 9) Vin –0.3 to AVCC +0.3 V Reference power supply voltage Vref –0.3 to AVCC +0.3 V Analog power supply voltage AVCC –0.
Section 25 Electrical Characteristics 25.2.2 DC Characteristics Table 25.14 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit — — V — VCC × 0.7 V — — V VCC × 0.9 — VCC +0.3 V RES, NMI, EMLE VCC × 0.9 — VCC +0.3 V Schmitt Ports 1, 2, and 4*2, VT– VCC × 0.
Section 25 Electrical Characteristics Table 25.15 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Symbol Min Typ Max Test Unit Conditions |Iin| — — 10.0 μA STBY, NMI, MD2 to MD0 — — 1.0 μA Ports 4 and 9 — — 1.0 μA Vin = 0.5 to AVCC –0.5 V | ITSI | — — 1.0 μA Vin = 0.5 to VCC –0.5 V –Ip 10 — 300 μA VCC = 3.
Section 25 Electrical Characteristics Item Reference power supply current During A/D and D/A conversion Min Typ AICC — 2.0 3.5 (3.0 V) mA — 0.01 0.5 μA 2.0 — — V Idle RAM standby voltage Test Unit Conditions Symbol VRAM Max Notes: 1. When the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current dissipation values are for VIHmin = VCC – 0.2 V and VILmax = 0.
Section 25 Electrical Characteristics Table 0.• Clock Timing Table 25.17 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 30.3 125 ns Figure 25.2 Clock pulse high width tCH 10 — ns Figure 25.
Section 25 Electrical Characteristics Table 0.• Control Signal Timing Table 25.18 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 — ns Figure 25.
Section 25 Electrical Characteristics Table 0.• Bus Timing Table 25.19 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions Address delay time tAD — 20 ns Address setup time 1 tAS1 0.5 × tcyc –13 — ns Figures 25.6 to 25.19 Address setup time 2 tAS2 1.
Section 25 Electrical Characteristics Item Symbol Min Max Unit Test Conditions Address read data access time 1 tAA1 — 1.0 × tcyc –20 ns Address read data access time 2 tAA2 — 1.5 × tcyc –20 ns Figures 25.6 to 25.19 Address read data access time 3 tAA3 — 2.0 × tcyc –20 ns Address read data access time 4 tAA4 — 2.5 × tcyc –20 ns Address read data access time 5 tAA5 — 3.0 × tcyc –20 ns Rev.6.00 Mar.
Section 25 Electrical Characteristics Table 25.20 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Max Unit Test Conditions WR delay time 1 tWRD1 — 15 ns WR delay time 2 tWRD2 — 15 ns Figures 25.6 to 25.19 WR pulse width 1 tWSW1 1.0 × tcyc –13 — ns WR pulse width 2 tWSW2 1.
Section 25 Electrical Characteristics Item Symbol Min Max Unit Test Conditions Precharge time 1 tPCH1 1.0 × tcyc –20 — ns Precharge time 2 tPCH2 1.5 × tcyc –20 — ns Figures 25.6 to 25.19 Self-refresh precharge time 1 tRPS1 2.5 × tcyc –20 — ns Self-refresh precharge time 2 tRPS2 3.
Section 25 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 25.22 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item I/O ports Symbol Min Output data delay time Max Unit Test Conditions Figure 25.
Section 25 Electrical Characteristics Item IIC2 Symbol Min Max Unit Test Conditions Figure 25.
Section 25 Electrical Characteristics 25.2.3 A/D Conversion Characteristics Table 25.23 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Min Typ Max Unit Resolution 10 10 10 Bit Conversion time 8.
Section 25 Electrical Characteristics 25.2.5 Flash Memory Characteristics Table 25.25 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 25 Electrical Characteristics Item Erasing Symbol Min Typ Max Unit Wait time after SWE bit setting*1 x 1 — — μs Wait time after ESU bit setting*1 y 100 — — μs Wait time after E bit setting*1*6 z — — 10 ms Wait time after 1 E bit clearing* α 10 — — μs Wait time after β ESU bit clearing*1 10 — — μs Wait time after EV bit setting*1 γ 20 — — μs Wait time after H'FF dummy 1 write* ε 2 — — μs Wait time after EV bit clearing*1 η 4 — — μs 100 — — μs
Section 25 Electrical Characteristics 25.3 Electrical Characteristics for 0.18 μm F-ZTAT Version 25.3.1 Absolute Maximum Ratings Table 25.26 lists the absolute maximum ratings. Table 25.26 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +4.3 V PLLVCC Input voltage (except ports 4 and 9) Vin −0.3 to VCC +0.3 V Input voltage (ports 4 and 9) Vin −0.3 to AVCC +0.3 V Reference power supply voltage Vref −0.3 to AVCC +0.
Section 25 Electrical Characteristics 25.3.2 DC Characteristics Table 25.27 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Typ. Max. Test Unit Conditions Schmitt Port 1, 2, 4*2, P50 trigger input to P53*2, PA4 to 2 voltage PA7* VT− Input high voltage Input low voltage VCC × 0.2 ⎯ ⎯ V + ⎯ ⎯ VCC × 0.
Section 25 Electrical Characteristics Table 25.28 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Symbol Min. Typ. Max. Test Unit Conditions |Iin| ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Port 4, Port 9 ⎯ ⎯ 1.0 μA Vin = 0.5 to AVCC −0.5 V | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.
Section 25 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions VCC rise slope*5 SVCC ⎯ ⎯ ⎯ ms/V Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current consumption values are for VIHmin = VCC − 0.2 V and VILmax = 0.2 V with all output pins unloaded and all input pull-up MOSs in the off state. 3. The values are for VRAM ≤ VCC < 3.
Section 25 Electrical Characteristics 25.3.3 AC Characteristics The clock, control signal, bus, DMAC, and on-chip peripheral function timings are shown below. The measurement conditions of the AC characteristics are shown in figure 25.1. (1) Clock Timing Table 25.30 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 25 Electrical Characteristics (2) Control Signal Timing Table 25.31 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ⎯ ns Figure 25.
Section 25 Electrical Characteristics (3) Bus Timing Table 25.32 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Address delay time TAD ⎯ 20 ns Address setup time 1 TAS1 0.5 × tcyc −13 ⎯ ns Figures 25.6 to 25.19 Address setup time 2 TAS2 1.
Section 25 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Address read data access time 1 TAA1 ⎯ 1.0 × tcyc −25 ns Address read data access time 2 TAA2 ⎯ 1.5 × tcyc −25 ns Figures 25.6 to 25.19 Address read data access time 3 TAA3 ⎯ 2.0 × tcyc −25 ns Address read data access time 4 TAA4 ⎯ 2.5 × tcyc −25 ns Address read data access time 5 TAA5 ⎯ 3.0 × tcyc −25 ns Rev.6.00 Mar.
Section 25 Electrical Characteristics Table 25.33 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions WR delay time 1 tWRD1 ⎯ 15 ns WR delay time 2 tWRD2 ⎯ 15 ns Figures 25.6 to 25.19 WR pulse width 1 tWSW1 1.0 × tcyc −13 ⎯ ns WR pulse width 2 tWSW2 1.
Section 25 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Precharge time 1 tPCH1 1.0 × tcyc −20 ⎯ ns Precharge time 2 tPCH2 1.5 × tcyc −20 ⎯ ns Figures 25.6 to 25.19 Self-refresh precharge time 1 tRPS1 2.5 × tcyc −20 ⎯ ns Self-refresh precharge time 2 tRPS2 3.
Section 25 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 25.35 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item I/O ports Symbol Min. Max. Unit Test Conditions Figure 25.
Section 25 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 25.38 IIC2 SCL input cycle time tSCL 12 tcyc +600 ⎯ ns Figure 25.
Section 25 Electrical Characteristics 25.3.4 A/D Conversion Characteristics Table 25.36 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 34 MHz, Ta = −20°C to +75°C (regular specifications), Ta = −40°C to +85°C (wide-range specifications) Item Min. Typ. Max. Unit Resolution 10 10 10 Bit Conversion time 7.
Section 25 Electrical Characteristics 25.3.6 Flash Memory Characteristics Table 25.38 Flash Memory Characteristics (0.18-μm F-ZTAT Version) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = 0°C to 75°C (Programming/Erasing Operating Temperature Range: Normal Specifications), Ta = 0°C to 85°C (Programming/Erasing Operating Temperature Range: Extended Temperature Range Specifications) Item Symbol Min. Typ. Max.
Section 25 Electrical Characteristics 25.4 Usage Note The F-ZTAT and masked ROM versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on.
Appendix Appendix A. I/O Port States in Each Pin State Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode 1, 2. 4, 7 T T Keep Keep I/O port Port 2 1, 2. 4, 7 T T Keep Keep I/O port P34 to P30 1, 2. 4, 7 T T Keep Keep I/O port P35/(OE) 1, 2.
Appendix Port Name PA7/A23/ CS7 MCU Operating Mode Reset Hardware Standby Mode 1, 2. 4, 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, CS output] [Address output] [CS output] T CS [Other than the above] [Address output] Keep A23 T [OPE = 1, CS output] H [OPE = 0, address output] [Other than the above] T I/O port [OPE = 1, address output] Keep [Other than the above] Keep PA6/A22 1, 2.
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode Port B 1, 2 L T Software Standby Mode Bus Release State [OPE = 0] T Program Execution State Sleep Mode T Address output [OPE = 1] A15 to A8 Keep 4 T T [OPE = 0, address output] T [OPE = 1, address output] Keep [Address output] T [Other than the above] Keep [Address output] A15 to A8 [Other than the above] I/O port [Other than the above] Keep 3, 7 T T [OPE = 0, address output] T [OPE = 1, address output] Keep [Addre
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode Port C 3, 7 T T Software Standby Mode Bus Release State [OPE = 0, address output] T [Address output] [OPE = 1, address output] Keep T [Other than the above] Keep Port E A7 to A0 [Other than the above] 1, 2, 4 T T T T D15 toD8 3, 7 T T [Data bus] T [Data bus] [Data bus] D15 to D8 [Other than the above] Keep [Other than the above] 1, 2, 4 3, 7 PF7/φ [Address output] I/O port [Other than the above] Keep Port D
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode PF6/AS 1, 2, 4 H T 3, 7 Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, AS output] [AS output] [AS output] T AS T [Other than the above] [Other than the above] Keep I/O port T RD, HWR [OPE = 0, RD, HWR output] [RD, HWR output] [RD, HWR output] T T RD, HWR [Other than the above] Keep [Other than the above] I/O port [LWR output] T [LWR output] LWR [OPE = 1, AS output] T H
Appendix Port Name PF2/LCAS/ CS6 MCU Operating Mode Reset Hardware Standby Mode 1, 2, 4, 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, LCAS (DQML) output] T [LCAS (DQML) output] T [LCAS (DQML) output] [OPE = 1, LCAS (DQML) output] H [CS output] T LCAS (DQML) [Other than the above] [CS output] CS Keep [Other than the above] I/O port [OPE = 0, UCAS (DQMU) output] T [UCAS (DQMU) output] T [UCAS (DQMU) output] [OPE = 1, UCAS (DQMU) output] H
Appendix Port Name MCU Operating Mode PG6/BREQ 1, 2, 4, 7 Reset Hardware Standby Mode Software Standby Mode Bus Release State T T [BREQ input] BREQ input T BREQ [Other than the above] Program Execution State Sleep Mode [BREQ input] BREQ [Other than the above] Keep I/O port PG5/BACK 1, 2, 4, 7 T T [BACK output] BACK BACK BACK [Other than the above] [Other than the above] Keep PG4/ BREQO/ CS4 1, 2, 4, 7 T T [BACK output] I/O port [BREQO output] BREQO [BREQO output] BREQO [O
Appendix Port Name MCU Operating Mode Reset Hardware Standby Mode PG0/CS0 1, 2 H T 3, 4, 7 T Software Standby Mode Bus Release State Program Execution State Sleep Mode [OPE = 0, CS output] [CS output] [CS output] T CS [Other than the above] [Other than the above] Keep I/O port H H* T [OPE = 1, CS output] H [Other than the above] Keep WDTOVF 1, 2, 3, 4, 7 H H H Legend: L: Low level H: High level Keep: Input port becomes high-impedance, output port retains state T: High impedance
Appendix B. Product Lineup Product Part No.
Appendix C. Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has Priority. JEITA Package Code P-TQFP120-14x14-0.40 RENESAS Code PTQP0120LA-A Previous Code TFP-120/TFP-120V MASS[Typ.] 0.5g HD *1 D 90 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 61 91 60 bp Reference Symbol D c c1 HE Dimension in Millimeters Min Nom Max 14 E 14 A2 1.00 *2 E b1 Terminal cross section 15.
Appendix JEITA Package Code P-QFP128-14x20-0.50 RENESAS Code PRQP0128KB-A Previous Code FP-128B/FP-128BV MASS[Typ.] 1.7g HD *1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D 102 65 103 64 Reference Symbol HE b1 c 39 128 1 Terminal cross section 38 ZD Nom E 14 A2 2.70 HD 21.8 22.0 22.2 HE 15.8 16.0 16.2 A1 0.00 0.10 0.25 bp 0.17 0.22 0.27 A2 A1 *3 bp M 0.20 0.12 c1 c A c y 3.
Appendix D. Bus State during Execution of Instructions Table D.1 shows the execution state of each instruction in this LSI. [Explanation of Table Contents] Order of execution Instruction 1 2 3 R:W 2nd 1 state of internal operation R:W EA 4 5 6 7 8 End of instruction Read the effective address in words. Read/write is not performed. Read the second word of the instruction that is being executed in words.
Appendix φ Address bus RD HWR, LWR High R: W 2nd Fetch of 3rd byte of instruction being executed Fetch of 4th byte of instruction being executed Internal operation R: W EA Fetch of 1st byte of Fetch of 2nd byte of brunch destination brunch destination instruction instruction Figure D.1 Timing of Address Bus, RD, HWR, and LWR (8-bit bus, 3-state access, no wait) Rev.6.00 Mar.
Appendix Table D.1 Execution State of Instructions Instruction 1 ADD.B #xx:8,Rd R:W NEXT 2 3 ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd R:W NEXT ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd R:W NEXT AND.B #xx:8,Rd R:W NEXT AND.B Rs,Rd R:W NEXT AND.W #xx:16,Rd R:W 2nd R:W: NEXT AND.W Rs,Rd R:W NEXT AND.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT AND.
Appendix Instruction 1 2 3 BAND #xx:3,@ERd R:W 2nd R:B EA R:W NEXT BAND #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT 4 5 6 7 8 9 BAND R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BAND R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BRA d:8 (BT d:8) R:W NEXT R:W EA BRN d:8 (BF d:8) R:W NEXT R:W EA BHI d:8 R:W NEXT R:W EA BLS d:8 R:W NEXT R:W EA BCC d:8 (BHS d:8) R:W NEXT R:W EA BCS d:8 (BLO d:8) R:W NEXT R:W EA BNE d:8 R:W NEXT R:W EA BEQ d:8 R:W NEXT R:W EA BVC d:8 R:W NEX
Appendix Instruction 1 2 3 BLE d:8 R:W NEXT R:W EA BRA d:16 (BT d:16) R:W 2nd 1 state of R:W EA BRN d:16 (BF d:16) R:W 2nd 1 state of R:W EA BHI d:16 R:W 2nd 1 state of R:W EA internal operation internal operation internal operation BLS d:16 R:W 2nd 1 state of R:W EA internal operation BCC d:16 (BHS d:16) R:W 2nd 1 state of R:W EA BCS d:16 (BLO d:16) R:W 2nd 1 state of R:W EA BNE d:16 R:W 2nd 1 state of R:W EA internal operation internal operation internal operation BEQ d:16 R:W 2nd
Appendix Instruction 1 2 3 BGE d:16 R:W 2nd 1 state of R:W EA 4 5 6 7 8 9 internal operation BLT d:16 R:W 2nd 1 state of R:W EA internal operation BGT d:16 R:W 2nd 1 state of R:W EA internal operation BLE d:16 R:W 2nd 1 state of R:W EA internal operation BCLR #xx:3,Rd R:W NEXT BCLR #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR R:W 2nd R:W 3rd R:B:M #xx:3,@aa:16 EA R:W:M NEXT BCLR R:W 2nd R:W 3rd R:W 4th R:B:M #xx:3,@aa:3
Appendix Instruction 1 2 3 4 5 6 BIAND R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BIAND R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BILD #xx:3,Rd R:W NEXT BILD #xx:3,@ERd R:W 2nd R:B EA R:W NEXT BILD #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT BILD R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BILD R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BIOR #xx:3,Rd R:W NEXT BIOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT BIOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT BIOR R:W 2nd R:W 3rd R:B EA R:W #xx:3,
Appendix Instruction 1 2 3 BIXOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT 4 5 6 7 8 9 BIXOR R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BIXOR R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BLD #xx:3,Rd R:W NEXT BLD #xx:3,@ERd R:W 2nd R:B EA R:W NEXT BLD #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT BLD R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BLD R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BNOT #xx:3,Rd R:W NEXT BNOT #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:8
Appendix Instruction 1 2 3 BOR #xx:3,@ERd R:W 2nd R:B EA R:W NEXT BOR #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT 4 5 6 BOR R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BOR R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BSET #xx:3,Rd R:W NEXT BSET #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BSET R:W 2nd R:W 3rd R:B:M #xx:3,@aa:16 EA R:W:M NEXT BSET R:W 2nd R:W 3rd R:W 4th R:B:M #xx:3,@aa:32 EA BSET Rn,Rd R:W NEXT BSET Rn,@ERd R:W
Appendix Instruction 1 2 BST #xx:3,@aa:8 R:W 2nd R:B:M EA 3 4 R:W:M NEXT W:B EA BST R:W 2nd R:W 3rd R:B:M #xx:3,@aa:16 EA R:W:M NEXT BST R:W 2nd R:W 3rd R:W 4th R:B:M #xx:3,@aa:32 EA BTST #xx:3,Rd R:W NEXT BTST #xx:3,@ERd R:W 2nd R:B EA R:W NEXT BTST #xx:3,@aa:8 R:W 2nd R:B EA R:W NEXT 5 6 7 8 9 W:B EA R:W:M NEXT W:B EA BTST R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BTST R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BTST Rn,Rd R:W NEXT BTST Rn,@ERd R:W 2nd R:B EA R:W NEX
Appendix Instruction 1 2 CLRMAC R:W NEXT 1 state of internal operation CMP.B #xx:8,Rd R:W NEXT 3 4 5 6 CMP.B Rs,Rd R:W NEXT CMP.W #xx:16,Rd R:W 2nd R:W NEXT CMP.W Rs,Rd R:W NEXT CMP.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT CMP.L ERs,ERd R:W NEXT DAA Rd R:W NEXT DAS Rd R:W NEXT DEC.B Rd R:W NEXT DEC.W #1/2,Rd R:W NEXT DEC.L #1/2,ERd R:W NEXT DIVXS.B Rs,Rd R:W 2nd R:W NEXT 11 states of internal operation DIVXS.W Rs,ERd R:W 2nd R:W NEXT 19 states of internal operation DIVXU.
Appendix Instruction 1 2 3 EXTS.W Rd R:W NEXT EXTS.L ERd R:W NEXT EXTU.W Rd R:W NEXT EXTU.L ERd R:W NEXT INC.B Rd R:W NEXT INC.W #1/2,Rd R:W NEXT INC.
Appendix Instruction 1 2 3 LDC @ERs,CCR R:W 2nd R:W NEXT R:W EA LDC @ERs,EXR R:W 2nd R:W NEXT R:W EA 4 LDC@(d:16,E R:W 2nd R:W 3rd R:W Rs),CCR NEXT R:W EA LDC@(d:16,E R:W 2nd R:W 3rd R:W Rs),EXR NEXT R:W EA 5 6 LDC@(d:32,E R:W 2nd R:W 3rd R:W 4th R:W 5th R:W Rs),CCR NEXT R:W EA LDC@(d:32,E R:W 2nd R:W 3rd R:W 4th R:W 5th R:W Rs),EXR NEXT R:W EA LDC R:W 2nd R:W @ERs+,CCR NEXT 1 state of R:W EA internal operation LDC @ERs+,EXR 1 state of R:W EA internal operation R:W 2nd R:W NEXT LDC
Appendix Instruction 1 2 LDMAC ERs,MACL R:W NEXT 1 state of internal operation MAC R:W 2nd R:W @ERn+,@ER NEXT m+ MOV.B #xx:8,Rd 3 4 R:W EAn R:W EAm 5 6 7 8 9 R:W NEXT MOV.B Rs,Rd R:W NEXT MOV.B @ERs,Rd R:W NEXT R:B EA MOV.B R:W 2nd R:W @(d:16,ERs), NEXT Rd R:B EA MOV.B R:W 2nd R:W 3rd R:W 4th R:W @(d:32,ERs), NEXT Rd MOV.B @ERs+,Rd R:W NEXT 1 state of R:B EA internal operation MOV.B @aa:8,Rd R:W NEXT R:B EA MOV.B @aa:16,Rd R:W 2nd R:W NEXT MOV.
Appendix Instruction 1 2 3 MOV.B Rs,@aa:16 R:W 2nd R:W NEXT MOV.B Rs,@aa:32 R:W 2nd R:W 3rd R:W NEXT MOV.W #xx:16,Rd R:W 2nd R:W NEXT 4 5 W:B EA W:B EA MOV.W Rs,Rd R:W NEXT MOV.W @ERs,Rd R:W NEXT R:W EA MOV.W R:W 2nd R:W @(d:16,ERs), NEXT Rd R:W EA MOV.W R:W 2nd R:W 3rd R:W 4th R:W @(d:32,ERs), NEXT Rd MOV.W @ERs+,Rd R:W NEXT MOV.W @aa:16,Rd R:W 2nd R:W NEXT MOV.W @aa:32,Rd R:W 2nd R:W 3rd R:W NEXT MOV.
Appendix Instruction 1 2 MOV.L ERs,ERd R:W NEXT MOV.L @ERs,ERd R:W 2nd R:W NEXT 3 4 R:W:M EA R:W EA+2 MOV.L R:W 2nd R:W 3rd R:W @(d:16,ERs), NEXT ERd R:W:M EA 5 R:W 2nd R:W NEXT 1 state of R:W:M internal EA operation MOV.L @aa:16,ERd R:W 2nd R:W 3rd R:W NEXT MOV.L @aa:32,ERd R:W 2nd R:W 3rd R:W 4th R:W NEXT MOV.L ERs,@ERd R:W 2nd R:W NEXT R:W:M EA 7 R:W:M EA R:W EA+2 8 9 R:W EA+2 MOV.L R:W 2nd R:W 3rd R:W 4th R:W 5th R:W @(d:32,ERs), NEXT ERd MOV.
Appendix Instruction 1 2 3 MULXU.B Rs,Rd R:W NEXT 2 status of internal operation MULXU.W Rs,ERd R:W NEXT 3 status of internal operation NEG.B Rd R:W NEXT NEG.W Rd R:W NEXT NEG.L ERd R:W NEXT NOP R:W NEXT NOT.B Rd R:W NEXT NOT.W Rd R:W NEXT NOT.L ERd R:W NEXT OR.B #xx:8,Rd R:W NEXT OR.B Rs,Rd R:W NEXT OR.W #xx:16,Rd R:W 2nd R:W NEXT OR.W Rs,Rd R:W NEXT OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT OR.
Appendix Instruction 1 2 POP.L ERn R:W 2nd R:W NEXT PUSH.W Rn R:W NEXT PUSH.L ERn R:W 2nd R:W NEXT ROTL.B Rd R:W NEXT 3 4 1 state of R:W:M internal EA operation 5 6 7 8 9 R:W EA+2 1 state of W:W EA internal operation 1 state of W:W:M internal EA operation W:W EA+2 ROTL.B #2,Rd R:W NEXT ROTL.W Rd R:W NEXT ROTL.W #2,Rd R:W NEXT ROTL.L ERd R:W NEXT ROTL.L #2,ERd R:W NEXT ROTR.B Rd R:W NEXT ROTR.B #2,Rd R:W NEXT ROTR.W Rd R:W NEXT ROTR.W #2,Rd R:W NEXT ROTR.
Appendix Instruction 1 ROTXL.W #2,Rd R:W NEXT 2 3 4 5 6 R:W Stack (EXR) R:W Stack (H) 3 R:W 1 state of R:W* Stack (L) internal R:W:M Stack (H) 3 R:W 1 state of R:W* Stack (L) internal ROTXL.L ERd R:W NEXT ROTXL.L #2,ERd R:W NEXT ROTXR.B Rd R:W NEXT ROTXR.B #2,Rd R:W NEXT ROTXR.W Rd R:W NEXT ROTXR.W #2,Rd R:W NEXT ROTXR.L ERd R:W NEXT ROTXR.L #2,ERd R:W NEXT RTE R:W NEXT RTS Advanced SHAL.B Rd R:W NEXT R:W NEXT SHAL.B #2,Rd R:W NEXT SHAL.W Rd R:W NEXT SHAL.
Appendix Instruction 1 2 3 4 5 6 7 8 9 SHAR.B #2,Rd R:W NEXT SHAR.W Rd R:W NEXT SHAR.W #2,Rd R:W NEXT SHAR.L ERd R:W NEXT SHAR.L #2,ERd R:W NEXT SHLL.B Rd R:W NEXT SHLL.B #2,Rd R:W NEXT SHLL.W Rd R:W NEXT SHLL.W #2,Rd R:W NEXT SHLL.L ERd R:W NEXT SHLL.L #2,ERd R:W NEXT SHLR.B Rd R:W NEXT SHLR.B #2,Rd R:W NEXT SHLR.W Rd R:W NEXT SHLR.W #2,Rd R:W NEXT SHLR.L ERd R:W NEXT SHLR.L #2,ERd R:W NEXT SLEEP R:W NEXT Internal operation: M Rev.6.00 Mar.
Appendix Instruction 1 2 3 4 5 6 STC CCR,Rd R:W NEXT STC EXR,Rd R:W NEXT STC CCR,@ERd R:W 2nd R:W NEXT W:W EA STC EXR,@ERd R:W 2nd R:W NEXT W:W EA STC CCR, R:W 2nd R:W 3rd R:W @(d:16,ERd) NEXT W:W EA STC EXR, R:W 2nd R:W 3rd R:W @(d:16,ERd) NEXT W:W EA STC CCR, R:W 2nd R:W 3rd R:W 4th R:W 5th R:W @(d:32,ERd) NEXT W:W EA STC EXR, R:W 2nd R:W 3rd R:W 4th R:W 5th R:W @(d:32,ERd) NEXT W:W EA STC CCR,@- R:W 2nd R:W ERd NEXT 1 state of W:W EA internal operation STC EXR,@- R:W 2nd R:W ERd NE
Appendix Instruction 1 2 STM.L (ERnERn+3), @-SP*8 R:W 2nd R:W NEXT STMAC MACH,ERd R:W NEXT STMAC MACL,ERd R:W NEXT 3 4 1 state of W:W:M internal Stack 2 operation (H)* 5 6 7 8 9 R:W:M VEC 6 R:W 1 state of R:W* VEC+2 internal W:W Stack (L) *2 SUB.B Rs,Rd R:W NEXT SUB.W #xx:16,Rd R:W 2nd R:W NEXT SUB.W Rs,Rd R:W NEXT SUB.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT SUB.
Appendix Instruction 1 XOR.L ERs,ERd R:W 2nd R:W NEXT XORC #xx:8,CCR R:W NEXT XORC #xx:8,EXR R:W 2nd R:W NEXT Reset R:W:M VEC R:W VEC+2 R:W*5 1 state of W:W W:W internal Stack (L) Stack operation (H) Advanced exception handling Interrupt Advanced exception handling 2 3 4 5 6 7 8 9 W:W Stack (EXR) R:W:M VEC 6 R:W 1 state of R:W* VEC+2 internal 1 state of R:W* internal operation 4 operation Notes: 1. EAs is the ER5 value and EAd the ER6 value.
Index Index 16-Bit Timer Pulse Unit.......................... 401 Buffer Operation................................. 447 Cascaded Operation ............................ 452 Input Capture Function ....................... 444 Phase Counting Mode......................... 459 PWM Modes....................................... 454 Synchronous Operation....................... 445 8-Bit Timer 16-Bit Counter Mode .......................... 520 Compare Match Count Mode .............
Index Traces.................................................... 84 Trap Instruction .................................... 85 Extended Control Register (EXR) ............ 31 Flash Memory......................................... 689 Boot Mode .......................................... 702 Erase/Erase-Verify.............................. 708 erasing units ........................................ 695 Error Protection .................................. 710 Hardware Protection ...........................
Index TGI2B................................................. 467 TGI3A................................................. 467 TGI3B................................................. 467 TGI3C................................................. 467 TGI3D................................................. 467 TGI4A................................................. 467 TGI4B................................................. 467 TGI5A................................................. 467 TGI5B............................
Index PADDR....................... 365, 841, 852, 864 PADR.......................... 366, 846, 858, 869 PAODR....................... 367, 842, 852, 864 PAPCR........................ 367, 841, 852, 864 PBDDR....................... 373, 841, 852, 864 PBDR.......................... 374, 846, 858, 869 PBPCR........................ 375, 841, 852, 864 PCDDR....................... 377, 841, 852, 864 PCDR.......................... 378, 846, 858, 869 PCPCR........................ 379, 841, 852, 864 PCR.............
Index FPCS................................................... 726 FTDAR ............................................... 726 FVACR............................................... 727 Reset ......................................................... 81 Serial Communication Interface ............. 541 Asynchronous Mode ........................... 576 bit rates ............................................... 564 Break................................................... 622 Clocked Synchronous Mode...............
Index Rev.6.00 Mar.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2368 Group Publication Date: 1st Edition, March 2002 Rev.6.00, March 18, 2009 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. ©2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2368 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0050-0600