Datasheet

Appendix B Internal I/O Registers
Rev.7.00 Feb. 14, 2007 page 959 of 1108
REJ09B0089-0700
MRB—DTC Mode Register B H'F800—H'FBFF DTC
0
1
After DTC data transfer ends, the CPU interrupt
is disabled unless the transfer counter is 0
After DTC data transfer ends, the CPU interrupt
is enabled
7
CHNE
Undefined
⎯
6
DISEL
Undefined
⎯
5
CHNS
Undefined
⎯
4
⎯
Undefined
⎯
3
⎯
Undefined
⎯
0
⎯
Undefined
⎯
2
⎯
Undefined
⎯
1
⎯
Undefined
⎯
Bit
Initial value
Read/Write
:
:
:
DTC Chain Transfer Enable
DTC Chain Transfer Select
CHNE
0
1
1
CHNS
⎯
0
1
Description
No chain transfer (At end of DTC data transfer, DTC waits
for activation)
Chain transfer every time
Chain transfer only when transfer counter = 0
DTC Interrupt Select
Reserved
Only 0 should be written to these bits
SAR—DTC Source Address Register H'F800—H'FBFF DTC
23
Bit
Initial value
Read/Write
:
:
:
22 21 20 19 43210- - -
- - -
- - -
- - -
Specifies DTC transfer data source address
Unde-
fined
⎯
Unde-
fined
⎯
Unde-
fined
⎯
Unde-
fined
⎯
Unde-
fined
⎯
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
⎯⎯⎯⎯⎯