Datasheet

Appendix A Instruction Set
Rev.7.00 Feb. 14, 2007 page 871 of 1108
REJ09B0089-0700
Addressing Mode/
Instruction Length (Bytes)
Operand Size
#xx
Rn
@ERn
@(d,ERn)
@-ERn/@ERn+
@aa
@(d,PC)
@@aa
Mnemonic
EXTS TAS MAC CLRMAC LDMAC STMAC
EXTS.W Rd W 2 EXTS.L ERd L 2 TAS @ERd
*3
B 4
MAC @ERn+, @ERm+ CLRMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC MACH,ERd STMAC MACL,ERd
(<bit 7> of Rd16)→ ⎯ ⎯ 0 ⎯ 1 (<bits 15 to 8> of Rd16) (<bit 15> of ERd32)→ ⎯ ⎯ 0 ⎯ 1 (<bits 31 to 16> of ERd32) @ERd-0→CCR set, (1)→ ⎯ ⎯ 0 ⎯ 4
(<bit 7> of @ERd) [2]
Operation
Condition Code
IHNZVC
Advanced
No. of States
*1
↔ ↔ ↔
↔ ↔ ↔
Cannot be used in the chip