Datasheet

Section 10 8-Bit Timers
Rev.7.00 Feb. 14, 2007 page 409 of 1108
REJ09B0089-0700
10.6.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 10.11 shows this operation.
φ
A
ddress TCNT address
Internal write signal
TCNT input clock
TCNT
NM
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 10.11 Contention between TCNT Write and Increment