Datasheet

Section 10 8-Bit Timers
Rev.7.00 Feb. 14, 2007 page 403 of 1108
REJ09B0089-0700
Timer Output Timing: When compare match A or B occurs, the timer output changes as
specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same,
change to 0, change to 1, or toggle.
Figure 10.5 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Figure 10.5 Timing of Timer Output
Timing of Compare Match Clear: The timer counter is cleared when compare match A or B
occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 10.6 shows the
timing of this operation.
φ
N H'00
Compare match
signal
TCNT
Figure 10.6 Timing of Compare Match Clear