Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)

Rev.7.00 Feb. 14, 2007 page 388 of 1108

REJ09B0089-0700

Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and

counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing

takes precedence.

Figure 9.56 shows the operation timing when a TGR compare match is specified as the clearing

source, and H'FFFF is set in TGR.

Counter

clear signal

TCNT input

clock

TCNT

TGF

Prohibited

TCFV flag

H'FFFF H'0000

Figure 9.56 Contention between Overflow and Counter Clearing