Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Feb. 14, 2007 page 385 of 1108
REJ09B0089-0700
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T
1
state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 9.53 shows the timing in this case.
Input capture
signal
Read signal
A
ddress
φ
TGR address
TGR
TGR read cycle
T
1
T
2
M
Internal
data bus
X M
Figure 9.53 Contention between TGR Read and Input Capture