Datasheet

Section 1 Overview
Rev.7.00 Feb. 14, 2007 page 2 of 1108
REJ09B0089-0700
Table 1.1 Overview
Item Specification
CPU
• General-register machine
⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
• High-speed operation suitable for realtime control
⎯ Maximum clock rate: 25 MHz
⎯ High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 40 ns (at 25-MHz operation)
16 × 16-bit register-register multiply: 800 ns (at 25-MHz operation)
32 ÷ 16-bit register-register divide: 800 ns (at 25-MHz operation)
• Instruction set suitable for high-speed operation
⎯ Sixty-five basic instructions
⎯ 8/16/32-bit move/arithmetic and logic instructions
⎯ Unsigned/signed multiply and divide instructions
⎯ Powerful bit-manipulation instructions
• CPU operating mode
⎯ Advanced mode: 16-Mbyte address space
Bus controller
• Address space divided into 8 areas, with bus specifications settable
independently for each area
• Chip select output possible for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• External bus release function
Data transfer
controller (DTC)
• Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation
source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
16-bit timer-pulse
unit (TPU)
• 6-channel 16-bit timer
• Pulse I/O processing capability for up to 16 pins
• Automatic 2-phase encoder count capability