Datasheet

Rev.7.00 Feb. 14, 2007 page xxv of xxxii
REJ09B0089-0700
14.1.3 Pin Configuration.................................................................................................533
14.1.4 Register Configuration.........................................................................................534
14.2 Register Descriptions........................................................................................................535
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................535
14.2.2 A/D Control/Status Register (ADCSR) ...............................................................536
14.2.3 A/D Control Register (ADCR) ............................................................................538
14.2.4 Module Stop Control Register (MSTPCR)..........................................................539
14.3 Interface to Bus Master.....................................................................................................540
14.4 Operation...........................................................................................................................541
14.4.1 Single Mode (SCAN = 0) ....................................................................................541
14.4.2 Scan Mode (SCAN = 1).......................................................................................543
14.4.3 Input Sampling and A/D Conversion Time..........................................................545
14.4.4 External Trigger Input Timing.............................................................................546
14.5 Interrupts...........................................................................................................................547
14.6 Usage Notes ......................................................................................................................548
Section 15 D/A Converter..................................................................................553
15.1 Overview...........................................................................................................................553
15.1.1 Features................................................................................................................553
15.1.2 Block Diagram.....................................................................................................554
15.1.3 Pin Configuration.................................................................................................555
15.1.4 Register Configuration.........................................................................................555
15.2 Register Descriptions........................................................................................................556
15.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) .......................................................556
15.2.2 D/A Control Registers 01 (DACR01)..................................................................556
15.2.3 Module Stop Control Register (MSTPCR)..........................................................558
15.3 Operation...........................................................................................................................559
Section 16 RAM ................................................................................................561
16.1 Overview...........................................................................................................................561
16.1.1 Block Diagram.....................................................................................................561
16.1.2 Register Configuration.........................................................................................562
16.2 Register Descriptions........................................................................................................562
16.2.1 System Control Register (SYSCR)......................................................................562
16.3 Operation...........................................................................................................................563
16.4 Usage Note........................................................................................................................563
Section 17 ROM ................................................................................................565
17.1 Overview...........................................................................................................................565
17.1.1 Block Diagram.....................................................................................................565