Datasheet

Section 7 Data Transfer Controller
Rev.7.00 Feb. 14, 2007 page 200 of 1108
REJ09B0089-0700
Interrupt Source
Origin of
Interrupt
Source
Vector
Number
Vector
Address
DTCE
*
Priority
TGI3A (GR3A compare match/
input capture)
TPU channel 3 48 H'0460 DTCEC5 High
TGI3B (GR3B compare match/
input capture)
49 H'0462 DTCEC4
TGI3C (GR3C compare match/
input capture)
50 H'0464 DTCEC3
TGI3D (GR3D compare match/
input capture)
51 H'0466 DTCEC2
TGI4A (GR4A compare match/
input capture)
TPU channel 4 56 H'0470 DTCEC1
TGI4B (GR4B compare match/
input capture)
57 H'0472 DTCEC0
TGI5A (GR5A compare match/
input capture)
TPU channel 5 60 H'0478 DTCED5
TGI5B (GR5B compare match/
input capture)
61 H'047A DTCED4
CMIA0 64 H'0480 DTCED3
CMIB0
8-bit timer
channel 0
65 H'0482 DTCED2
CMIA1 68 H'0488 DTCED1
CMIB1
8-bit timer
channel 1
69 H'048A DTCED0
RXI0 (receive-data-full 0) 81 H'04A2 DTCEE3
TXI0 (transmit-data-empty 0)
SCI channel 0
82 H'04A4 DTCEE2
RXI1 (receive-data-full 1) SCI channel 1 85 H'04AA DTCEE1
TXI1 (transmit-data-empty 1) 86 H'04AC DTCEE0 Low
Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0.