Datasheet

Section 7 Data Transfer Controller
Rev.7.00 Feb. 14, 2007 page 189 of 1108
REJ09B0089-0700
7.2.3 DTC Source Address Register (SAR)
Bit : 23 22 21 20 19 – – – 4 3 2 1 0
– – –
Initial value :
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
– – – Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
R/W : — — — — — – – – — — — — —
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4 DTC Destination Address Register (DAR)
Bit : 23 22 21 20 19 – – – 4 3 2 1 0
– – –
Initial value :
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
– – – Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
R/W : — — — — — – – – — — — — —
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
7.2.5 DTC Transfer Count Register A (CRA)
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value :
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
Unde-
fined
R/W : — — — — — — — — — — — — — — — —
←⎯⎯⎯⎯⎯⎯ CRAH ⎯⎯⎯⎯⎯→ ←⎯⎯⎯⎯⎯⎯⎯ CRAL ⎯⎯⎯⎯⎯⎯→
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA register is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is